Intellectual property core implementation of decision trees

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© The Institution of Engineering and Technology
Published 30/07/2012

Abstract

Several soft intellectual property (IP) core implementations of decision trees (axis-parallel, oblique and nonlinear) based on the concept of universal node (UN) and sequence of UNs are presented. Proposed IP cores are suitable for implementation in both field programmable gate arrays and application specific integrated circuits. Developed IP cores can be easily customised in order to fit a wide variety of application requirements, fulfilling their role as general purpose building blocks for SoC designs. Experimental results obtained on 23 data sets of standard UCI machine learning repository database suggest that the proposed architecture based on the sequence of UNs requires on average 56% less hardware resources compared with previously proposed architectures, having the same throughput.

Inspec keywords: industrial property; system-on-chip; field programmable gate arrays; decision trees; application specific integrated circuits

Other keywords: application specific integrated circuits; IP cores; decision trees; standard UCI machine learning repository database; universal node; intellectual property; SoC; field programmable gate arrays

Subjects: Logic and switching circuits; Microprocessor chips; Logic circuits; Microprocessors and microcomputers; Combinatorial mathematics; Combinatorial mathematics

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