Radio-frequency front-end for 5 GHz wireless local area network transceivers

Access Full Text

Radio-frequency front-end for 5 GHz wireless local area network transceivers

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A transceiver front-end for 5 GHz wireless local area network applications has been designed and implemented in a low-cost 46 GHz fT pure-silicon bipolar technology. The transceiver front-end adopts a superheterodyne sliding-IF architecture and consists of a down-converter, an up-converter and an LO frequency synthesiser. By exploiting a 1 bit variable-gain low-noise amplifier, the down-converter is able to provide an excellent noise figure of 4 dB while ensuring an input 1 dB compression point of −10 dBm with a current consumption of 25 mA from a 3 V supply voltage. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1 dB compression point of 5.3 dBm although consuming only 45 mA from a 3 V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35 dB dynamic range. The LO frequency synthesiser is implemented by means of an integer-N phase-locked loop. It features a phase noise of −117 dBc/Hz at 1 MHz offset from the centre frequency of 4.1 GHz and exhibits a tuning range of 1.2 GHz, from 3.47 to 4.65 GHz. The LO frequency synthesiser draws 20 mA from a 3 V supply voltage.

Inspec keywords: low noise amplifiers; bipolar MMIC; transceivers; superheterodyne receivers; wireless LAN; frequency synthesizers; microwave amplifiers

Other keywords: frequency 46 GHz; current 45 mA; transceiver front-end; microwave amplifiers; voltage 3 V; current 20 mA to 25 mA; low-noise amplifier; frequency 5 GHz; noise figure 4 dB; current-reuse variable-gain up-converter; superheterodyne sliding-IF architecture; frequency 3.47 GHz to 4.65 GHz; frequency synthesiser; wireless local area network; bipolar MMIC

Subjects: Bipolar integrated circuits; Microwave integrated circuits; Radio links and equipment; Amplifiers; Signal generators

References

    1. 1)
      • Carrara, F., Italia, A., Scuderi, A.: `Low-power RF circuits for multi-standard WLAN transceivers', IEEE European Microwave Integrated Circuit Conf., October 2007, p. 235–238.
    2. 2)
    3. 3)
      • W.F. Egan . (1981) Frequency synthesis by phase lock.
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
      • Heinspan, H., Soyeur, M.: `A fully integrated 5 GHz frequency synthesizer in SiGe BiCMOS', Proc. IEEE Bipolar/BiCMOS Circuits Technol. Meeting, September 1999, p. 165–168.
    9. 9)
      • F.M. Gardner . (1979) Phaselock techniques.
    10. 10)
      • Carrara, F., Palmisano, G.: `Variable-gain up-converter with current reuse for WCDMA wireless transmitters', Proc. IEEE Int. Symp. Circuits and Systems, May 2005, p. 3247–3250.
    11. 11)
    12. 12)
    13. 13)
      • C. Lam , B. RazavI . A 2.6/5.2 GHz frequency synthesizer in 0.4 µm CMOS technology. IEEE J. Solid-State Circuits , 788 - 794
    14. 14)
    15. 15)
    16. 16)
    17. 17)
      • Girlando, G., Copani, T., Smerzi, S.A., Castorina, A., Palmisano, G.: `A 12 GHz silicon bipolar receiver for digital satellite applications', Int. Solid-State Circuits Conf. Tech. Dig., February 2004, p. 276–277.
    18. 18)
    19. 19)
    20. 20)
    21. 21)
      • Palmisano, G., Pennisi, S.: `Low noise amplifier with programmable gain', US Patent 6181206, June 1999.
    22. 22)
      • `High speed physical layer in the 5 GHz band', IEEE Std 802.11a-1999, September 1999.
    23. 23)
      • Alam, S.K., Degroat, J.: `A CMOS variable gain front-end for WCDMA receiver', IEEE Int. Symp. Circuits and Systems, May 2007, p. 1457–1460.
    24. 24)
    25. 25)
      • Pennisi, S., Scaccianoce, S., Palmisano, G.: `A new design approach for variable-gain low-noise amplifiers', IEEE Radio Frequency Integrated Circuits Symp. Digest, June 2000, p. 139–142.
    26. 26)
    27. 27)
      • Physical (PHY) layer: ETSI TS 101 475, version 1.3.1, December 2001, Broadband Radio Access Networks (BRAN); HIPERLAN Type 2;.
    28. 28)
      • Copani, T., Smerzi, S.A., Girlando, G., Palmisano, G.: `Transformer-based VCO for both phase noise and tuning range improvement in bipolar technology', US Patent 7245190, February 2005.
    29. 29)
      • Simon, M.: `An 802.11a/b/g RF transceiver in an SoC', Int. Solid-State Circuits Conf. Tech. Dig., February 2007, p. 562–563.
    30. 30)
    31. 31)
      • Maeda, T.: `A low-power dual-band triple-mode WLAN CMOS transceiver', Int. Solid-State Circuits Conf. Tech. Dig., February 2005, p. 100–101.
    32. 32)
      • Nathawad, L.: `An IEEE 802.11a/b/g SoC for embedded WLAN applications', Int. Solid-State Circuits Conf. Tech. Dig., February 2006, p. 364–365.
    33. 33)
    34. 34)
    35. 35)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20080018
Loading

Related content

content/journals/10.1049/iet-cds_20080018
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading