© The Institution of Engineering and Technology
A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages.
References
-
-
1)
-
Bui, H.T., Savaria, Y.: `High speed differential pulse-width control loop based on frequency-to-voltage converters', GLSVLSI'06, April 30–May 2 2006, p. 53–56.
-
2)
-
Y.C. Yang ,
S.A. Yu ,
T. Wang ,
S.S. Lu
.
A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell.
IEEE Microw. Wirel. Compon. Lett.
,
11 ,
754 -
756
-
3)
-
Wang, Y.M., Wang, J.S.: `An all-digital 50% duty-cycle corrector', Proc. Int. Symp. Circuits and Systems, May 2004, 2, p. II - 925–928.
-
4)
-
Khadanga, S.: `Synchronous programmable divider design for PLL using 0.18 µm CMOS technology', Proc. 3rd IEEE Int. Workshop on System-on-Chip for Real-Time Applications, 2003, p. 281–286.
-
5)
-
Y.-C. Yang ,
S.-A. Yu ,
Y.-H. Liu ,
T. Wang ,
S.-S. Lu
.
A quantization noise suppression technique for ΔΣ fractional-N frequency synthesizers.
IEEE J. Solid-State Circuits
,
11 ,
2500 -
2511
-
6)
-
Guermandi, D., Franchi, E., Gnudi, A., Baccarani, G.: `A CMOS programmable divider for RF multistandard frequency synthesizers', Proc. 28th European Solid-State Circuits Conf., 2002, p. 843–846.
-
7)
-
R.E. Best
.
(2003)
Phase-locked loops design, simulation, and applications.
-
8)
-
Yang, W.B., Kuo, S.C., Chu, Y.H., Cheng, K.H.: `The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle', Proc. 2005 European Conf. Circuit Theory and Design, 2005, 3, p. III/193–III/196.
-
9)
-
X.P. Yu ,
M.A. Do ,
L. Jia ,
J.G. Ma ,
K.S. Yeo
.
Design of low power wide-band high resolution programmable frequency divider.
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
,
9 ,
1098 -
1103
-
10)
-
F. Rezzi ,
F. Montecchi ,
R. Castello
.
A PLL-based frequency synthesizer for 160 MHz double-sampled SC filters.
IEEE J. Solid-State Circuits
,
10 ,
1560 -
1564
-
11)
-
S. Karthikeyan
.
Clock duty cycle adjuster circuit for switched capacitor circuits.
Electronics Letters
,
18 ,
1008 -
1009
-
12)
-
http://www.nodna.com/fileadmin/download/INEX/Robo-51/AT89 C51AC2manual.pdf accessed August 2007.
-
13)
-
Li, L., Chen, J.H., Chang, R.C.: `A low jitter delay-locked loop with a realignment duty cycle corrector', Proc. IEEE Int. SOC. Conf., September 2005, p. 73–76.
-
14)
-
C.S. Vaucher ,
I. Ferencic ,
M. Locher ,
S. Sedvallson ,
U. Voegeli ,
Z. Wang
.
A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology.
IEEE J. Solid-State Circuits
,
7 ,
1039 -
1045
-
15)
-
http://datasheets.maxim-ic.com/en/ds/MXB7843.pdf, accessed August 2007.
-
16)
-
Wang, H.M.: `A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 µm CMOS', IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, February 2000, p. 196–197.
-
17)
-
S. Lee ,
H. Park
.
A CMOS high-speed wide-range programmable counter.
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
,
9 ,
638 -
642
-
18)
-
T. Gawa ,
K. Taniguchi
.
A 50% duty-cycle correction circuit for PLL output.
IEEE Int. Symp. Circuits Syst.
,
IV -
21
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20070150
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