State-of-the-art technologies and devices for high-voltage integrated circuits

Access Full Text

State-of-the-art technologies and devices for high-voltage integrated circuits

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

The current status of high-voltage power semiconductor devices and technologies for high-voltage integrated circuits is reviewed and the new trends in this field are discussed. The paper focuses on the concepts of the novel reduced surface field and state-of-the-art silicon technologies such as high-voltage silicon on insulator, which are expected to play an increasingly important role in power system on-chip manufacturing. Lateral devices such as LDMOSFETs, superjunctions and lateral insulated gate bipolar transistors are discussed. The paper also touches on emerging technologies such as unified MEMS-IC for enhanced breakdown capability and isolation. Finally, an overview of the fierce fight of technology survival in terms of specific on-state resistance against breakdown voltage is given.

Inspec keywords: silicon-on-insulator; power integrated circuits

Other keywords: state of the art technologies; high voltage integrated circuits; MEMS IC; lateral devices; surface field; state resistance; high voltage power semiconductor devices; silicon technologies; silicon on insulator; breakdown voltage; breakdown capability

Subjects: Power semiconductor devices; Power electronics, supply and supervisory circuits; Power integrated circuits

References

    1. 1)
      • Kurosaki, T., Shishido, H., Kitada, M., Oshima, K., Kunori, S., Sugai, A.: `200V multi RESURF trench MOSFET (MR-TMOS)', Proc. ISPSD2003, 2003, p. 211–214.
    2. 2)
      • T. Fujihira , Y. Miyasaka . Simulated superior performances of semiconductor superjunction devices. ISPSD 98
    3. 3)
      • H. Sakuma , T. Kuriyama , T. Suzuki . (1979) A high voltage offset gate SOS/MOS transistor.
    4. 4)
      • S. Hardikar , R. Tadikonda , D. Green , K.V. Vershinin , E.M. Sankara Narayanan . Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping. IEEE Trans. Electron Devices , 12 , 2223 - 2228
    5. 5)
      • Takahashi, K., Kuribayashi, H., Kawashima, T., Wakimoto, S., Mochizuki, K., Nakazawa, H.: `20 mohm-cm', Proc. ISPSD2006, 2006, p. 305.
    6. 6)
      • Miura, Y.: `High performance superjunction UMOSFETs with split P-columns fabricated by multi-ion-implantations', Proc. ISPSD, 2005, p. 39–42.
    7. 7)
      • Iwamoto, S., Takahashi, K., Kuribayashi, H., Wakimoto, S., Mochizuki, K., Nakazawa, H.: `Above 500 V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth', Proc. ISPSD2005, 2005, p. 31.
    8. 8)
      • H.M.J. Vaes , J.A. Appels . High voltage high current lateral devices (RESURF devices). IEDM Technical Digest , 87 - 90
    9. 9)
      • Minato, T., Nitta, T., Uenisi, A., Yanao, M., Harada, M., Hine, S.: `Which is cooler, trench or multi-epitaxy?', Proc. ISPSD2000, 2000, p. 73–76.
    10. 10)
      • Disney, D.R., Paul, A.K., Darwish, M., Basescki, R., Rumennik, V.: `A new lateral MOSFET with dual conduction path', Proc. ISPSD, 2001, p. 399.
    11. 11)
      • Shoichi, Y., Shibata, T., Nogami, S., Yamaoka, T., Hattori, Y., Yamaguchi, H.: `200 V super junction MOSFET fabricated by high aspect ratio trench filling', Proc. ISPSD2006, 2006, p. 63.
    12. 12)
      • Kawai, F., Onishi, T., Kamiya, T., Ishimabushi, H., Eguchi, H., Nakahama, K., Aoki, H., Hamada, K.: `Multi-voltage SOI-BiCDMOS for 14V & 42V automotive applications', Proc. ISPSD2004, 2004, p. 165.
    13. 13)
      • Saito, W., Omura, I., Aida, S., Koduki, S., Izumisawa, M., Yoshioka, H., Okumura, H., Yamaguchi, M., Ogura, T.: `A 15.5 mΩcm2-680 V superjunction MOSFET reduced on-resistance by lateral pitch narrowing', Proc. ISPSD2006, 2006, p. 300.
    14. 14)
      • Ruba, M.L.: `A 600 V, 8.7 ohm-mm', Proc. ISPSD, 2006, p. 305.
    15. 15)
      • Saito, W., Omura, I., Aida, S., Koduki, S., Izumisawa, M., Yoshioka, H., Ogura, T.: `A 20 m-ohm-cm2 600V-class superjunction MOSFET', Proc. ISPSD2004, 2004, p. 459.
    16. 16)
      • Ludikhuize, A.W.: `A review of RESURF technology', Proc. ISPSD 2000, 2000, p. 11–18.
    17. 17)
      • Ludikhuize, A.W., Van der Pol, J.A., Padiy, A., Ooms, E.R., Van Kessel, P.: `Extended (180 V) voltage in 0.6 µm thin-layer-SOI A-BCD-3 technology on 1 µm BOX for display, automotive and consumer applications', Proc. ISPSD, 2002, p. 77–80.
    18. 18)
      • G. Deboy . (1998) A new generation of high voltage MOSFETs breaks the circuit line of silicon.
    19. 19)
      • Contiero, C., Galbiati, P., Palmieri, M., Ricotti, G., Stella, R.: `Smart power approaches VLSI complexity', Proc. ISPSD, 1998, p. 11.
    20. 20)
      • F. Udrea , A. Popescu , W.I. Milne . The 3D RESURF double-gate MOSFET: a revolutionary power device concept. Electron. Lett. , 8
    21. 21)
      • Y. Sugawara , T. Kamei . Field reduction regions for compact high-voltage ICs. IEEE Trans. Electron Devices , 1816 - 1821
    22. 22)
      • Rub, M., Bar, M., Deboy, G., Niedernostheide, F.-J., Schmitt, M., Schulze, H.J., Willmeroth, A.: `550V superjunction 3.9ohme-mm2 transistor formed by 25 MeV masked boron implantation', Proc. ISPSD2004, 2004, p. 455.
    23. 23)
      • Fujishima, N., Takeda, H.: `A novel field-plate structure under high voltage interconnections', Proc. 1990 Int. Symp. Power Semiconductor Devices and Integrated Circuits, , Tokyo, Japan, p. 91–96.
    24. 24)
      • Rocherfort, C., Van Dalen, R., Duhayon, N., Vandervorst, W.: `Manufacturing of high aspect-ratio p-n junctions using vapor phase doping for application in multi-Resurf devices', Proc. ISPSD2002, 2002, p. 237.
    25. 25)
      • Hattori, Y., Nakashima, K., Kuwahara, M., Yoshida, T., Yamauchi, S., Yamaguchi, H.: `Design of a 200 V super junction MOSFET with nbuffer regions and its fabrication by trench filling', Proc. ISPSD2004, 2004, p. 189.
    26. 26)
      • R. Ng , F. Udrea , G.A.J. Amaratunga . An analytical model for the 3D-RESURF effect. Solid State Electron. , 10 , 1753 - 1764
    27. 27)
      • www.camsemi.com.
    28. 28)
      • R. Ng . Lateral unbalanced super junction (USJ)/3D RESURF for high breakdown voltage on SOI.
    29. 29)
      • Nehrer, W.: `Power BiCMOS process with high voltage device implementation for 20V mixed signal circuit applications', Proc. ISPSD, 2001, p. 263–266.
    30. 30)
      • Nitta, T., Yanagi, S., Miyajima, T., Furuya, K., Otsu, Y., Onoda, H., Hatasako, K.: `Wide voltage power device implementation in 0.25 µm SOI BiC-DMOS', Proc. ISPSD06, 2006, p. 341.
    31. 31)
      • B. Murari , F. Bertotti , G.A. Vignola . (2002) Smart power ICs.
    32. 32)
      • Van Dalen, R.L.: `Electrical characterization of vertical vapor phase doped (VPD) RESURF MOSFETs', Proc. ISPSD, 2004, p. 451–454.
    33. 33)
      • Wessels, P., Swanenberg, M.: `Advanced 100 V, 0.13 µm BCD process for next generation automotive applications', Proc. ISPSD06, 2006, p. 197–200.
    34. 34)
      • J.A. Appels , H.M.J. Vaes . High voltage thin layer devices (RESURF devices). IEDM Technical Digest
    35. 35)
      • F. Udrea , T. Trajkovic , G.A.J. Amaratunga . Membrane high voltage devices – a milestone concept in power ICs. IEDM , 451 - 454
    36. 36)
      • Contiero, C., Andreini, A., Galbiati, P.: `Roadmap differentiation and emerging trends in BCD technology', Proc. ESSDERC, 2002, p. 275.
    37. 37)
    38. 38)
      • Udrea, F., Amaratunga, G.A.J.: US patent 6,703,684, 2004.
    39. 39)
      • Udrea, F.: `Ultra-fast LIGBTs and superjunction devices in membrane technology', Proc. ISPSD, 2005, p. 267–270.
    40. 40)
      • Letavic, T., Arnold, E., Simpson, M., Aquino, R., Bhimnathwala, H., Egloff, R., Emmerik, A., Wong, S., Mukherjee, S.: `High performance 600 V smart power technology based on thin layer silicon-on-insulator', Proc. ISPSD'97, 1997, p. 49–52.
    41. 41)
      • Kubota, T., Watanabe, K., Karouji, K., Ueno, M., Kawaguchi, Y., Nakagawa, A.: `Cost effective approach in LDMOS with partial 0.35 µm design into conventional 0.6 µm process', Proc. ISPSD, 2003, p. 245–248.
    42. 42)
      • S. Merchant . (1991) Realization of high breakdown voltage (>700 V) in thin SOI devices.
    43. 43)
      • Yamaguchi, H., Urakami, Y., Sakakibara, J.: `Breakthrough of on-resistance Si limit by super 3D MOSFET under 100 V breakdown voltage', Proc. ISPSD2006, 2006, p. 65.
    44. 44)
      • Fujihima, N., Saito, M., Kitamura, A., Urano, Y., Tada, G., Tsuruta, Y.: `A 700 V lateral power MOSFET with narrow gap double metal field plates realizing low on-resistance and long-term stability of performance', Proc. ISPSD, 2001, p. 255–258.
    45. 45)
      • S. Krishna , J. Kuo , I.S. Gaeta . An analog technology integrates bipolar, MOS and high volatge DMOS transistors. IEEE Trans. Electron Devices , 89 - 96
    46. 46)
      • M. Saggio . Mdmesh: innovative technology for high voltage Power MOSFETs.
    47. 47)
      • Moens, P., Bolognesi, D., Delobel, L., Villanueva, D., Hakim, H., Trinh, S.C.: `13T80: a 0.35 µm based system-on-chip technology for 42 V battery automotive applications', Proc. ISPSD, 2002, p. 225–228.
    48. 48)
      • Udrea, F.: US patent 611 289, .
    49. 49)
      • Letavic, T., Petruzzello, J., Claes, J., Eggenkamp, P., Janssen, E., Van der Wal, A.: `650 V SOI LIGBT for switch-mode power supply application', Proc. ISPSD2006, 2006, p. 357.
    50. 50)
      • Udrea, F., Amaratunga, G.A.J.: US Patent 6, 566, 240, .
    51. 51)
      • P.K.T. Mok , C.A.T. Salama . Interconnect induced breakdown in HVIC's. Electrochem. Soc. Spring Meeting , 206 - 217
    52. 52)
      • M.F. Chang . Lateral HVIC with 1200 V bipolar and field effect devices. IEEE Trans. Electron Devices , 1992 - 2001
    53. 53)
      • Takaya, H.: `Floating island and thick bottom oxide trench gate MOSFET (FITMOS)', Proc. ISPSD, 2005, p. 43–46.
    54. 54)
      • Y. Koishikawa . Double RESURF device technology for power ICs. NEC Res. Dev. , 4 , 438 - 443
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20070025
Loading

Related content

content/journals/10.1049/iet-cds_20070025
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading