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Low-voltage superjunction technology

Low-voltage superjunction technology

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Published

The scalability of superjunction and superfield power MOSFET technologies to breakdown voltage lower than 250 V is investigated. The influence of device geometry and process architecture on the switching figures-of-merit of these relatively new classes of power switches with a breakdown voltage rating of 80 V is presented. The current flow and field distributions inside these devices are described. Using Gauss's law, the field-induced compensation of the doping density in the drift region during the blocking state of both superjunction and superfield MOSFETs is calculated from the knowledge of the lateral field distributions. It is shown that the problem associated with imperfect charge compensation at the edge of the die for a superfield effect power MOSFET structure can be avoided by using an unconventional racetrack layout design.

Inspec keywords: power MOSFET; power semiconductor switches

Other keywords: superjunction technology; superfield power MOSFET; breakdown voltage; field distribution; Gauss's law; power switches

Subjects: Relays and switches; Power semiconductor devices; Insulated gate field effect transistors

References

    1. 1)
      • B.J. Baliga . (1996) Power semiconductor devices.
    2. 2)
    3. 3)
      • A. Rusu , C. Bulucea . Deep depletion breakdown voltage of SiO2/Si MOS capacitors. IEEE Trans. Electron Devices , 201 - 205
    4. 4)
      • Baliga, B.J.: `Trends us power devices', Proc. 18th Int. Symp. Power Semiconductor Devices and ICs, 1998, p. 5.
    5. 5)
      • Coe, D.J.: `High voltage semiconductor devices', European Patent EP 0053854 B1, 1982.
    6. 6)
      • M. Rub , M. Bar , G. Deml . (2006) A 600 V 8.7 Ω.mm.
    7. 7)
      • Shenoy, P., Bhalla, A., Dolny, M.G.: `Analysis of the effect of charge imbalance on the static and dynamic characteristic of super junction MOSFET', Proc. ISPSD, 1999, p. 99.
    8. 8)
      • D.N. Pattanayak , B. Yuming , K. Owyang . (2006) Low voltage super junction technology.
    9. 9)
    10. 10)
      • S. Yamauchi , T. Shibata , S. Nogami , T. Yamaoka , Y. Hattori , H. Yamaguchi . (2006) 200 V super junction MOSFET fabricated by high aspect ratio trench filing.
    11. 11)
    12. 12)
      • A.W. Ludikhuize . (2000) A review of RESURF technology.
    13. 13)
      • G. Deboy , M. Marz , J.-P. Stengl , H. Strack , J. Tihanyi , H. Weber . (1998) A new generation of high voltage MOSFETs breaks the limit line of silicon.
    14. 14)
      • A.G.M. Strollo , E. Napoli . Optimal on-resistance versus breakdown voltage tradeoff in super junction power devices: a novel analytical model. IEEE Trans. Electron Devices
    15. 15)
      • Saito, W., Omura, I., Aida, S.: `A 15.5 mΩ cm', Proc. 18th Int. Symp, 2006, p. 293, Power Semiconductor Devices and ICs.
    16. 16)
      • Temple, V.A.K.: `Semiconductor devices exhibiting minimum on resistance', US Patent 4941026, 1990.
    17. 17)
      • I. Yoshida , M. Kubo , S. Ochi . A high power MOSFET with a vertical drain electrode and meshed gate structure. IEDM Tech. Digest
    18. 18)
      • C. Hu . Optimum doping profile for minimum Ohmic resistance and high breakdown voltage. IEEE Trans. Electron. Devices , 243 - 244
    19. 19)
      • Gajda, M.A., Hodgskiss, S.W., Mounfield, L.A., Irwin, N.T.: `Industrialization of Resurf Stepped Oxide Technology for Power Transistors', Proc. 18th Int. Symp. Power Semiconductor Devices and ICs, 2006, p. 109.
    20. 20)
      • F. Udrea , T. Trajkovic , J. Thomson . (2001) Ultra-high voltage device termination using the 3D RESURF (super-junction) concept-experimental demonstration at 6.5 kV.
    21. 21)
      • C. Liang , K.P. Gan , G.S. Samudra . Oxide-bypassed VDMOS (OBVDMOS): an alternative to super junction high voltage MOS power devices. IEEE Electron Device Lett.
    22. 22)
      • W. Fulop . Calculations of avalanche breakdown voltages of silicon p-n junctions. Solid State Electron. , 39 - 43
    23. 23)
      • Pattanayak, D.N., Yuming, B., Terrill, K.: `Super trench MOSFET including buried source electrode and method of fabricating the same', US Patent 7183610, 2007.
    24. 24)
    25. 25)
      • H. Sakuma , T. Kuriyama , T. Suzuki . (1979) A high voltage offset-gate SOS/MOS transistor.
    26. 26)
      • D.A. Grant , J. Gowar . (1989) Power MOSFETs.
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