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The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose–Chaudhiri–Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.
References
-
-
1)
-
Chen, Y., Parhi, K.K.: `Area efficient parallel decoder architecture for long BCH codes', IEEE Int. Conf. Acoustics, Speech, and Signal Processing, May 2004, p. V-73–V-76.
-
2)
-
Rossi, D., Metra, C., Ricco, B.: `Fast and compact error correcting scheme for reliable multilevel flash memories', Proc. Eighth IEEE Int. On-Line Testing Workshop, July 2002, p. 221–225.
-
3)
-
Calligaro, C., Gastaldi, R., Manstretta, A., Torelli, G.: `A high-speed parallel sensing scheme for multi-level nonvolatile memories', Proc. Int. Workshop on Memory Technology, Design and Testing, August 1997, p. 96–101.
-
4)
-
A. Silvagni ,
G. Fusillo ,
R. Ravasio ,
M. Picca ,
S. Zanardi
.
An overview of logic architectures inside Flash memory devices.
Proc. IEEE
,
569 -
580
-
5)
-
G. Servalli
.
A 65nm NOR flash technology with 0.042 µm2 cell size for high performance multilevel application.
IEEE Int. Electron Devices Meeting
,
849 -
852
-
6)
-
T. Hara
.
A 146-mm2 8-Gb multi-level NAND flash memory with 70-nm CMOS technology.
IEEE J. Solid-State Circuits
,
161 -
169
-
7)
-
R.E. Blahut
.
(2003)
Algebraic codes for data transmission.
-
8)
-
H.-L. Lou ,
C.E.W. -Sundberg
.
Increasing storage capacity in multilevel memory cells by means of communications and signal processing techniques.
IEE Proc., Circuits Devices Syst.
,
229 -
236
-
9)
-
Sim, S.-P.: `A 90 nm generation NOR flash multilevel cell (MLC) with 0.44 µm', IEEE VLSI-TSA Int. Symp. on VLSI Technology, April 2005, p. 35–36.
-
10)
-
S. Gregori ,
A. Cabrini ,
O. Khouri ,
G. Torelli
.
On-chip error correcting techniques for new-generation Flash memories.
Proc. IEEE
,
602 -
616
-
11)
-
Sun, F., Devarajan, S., Rose, K., Zhang, T.: `Multilevel flash memory on-chip error correction based on trellis coded modulation', IEEE Int. Symp. Circuits and Systems (ISCAS), May 2006.
-
12)
-
B. Ricco
.
Nonvolatile multilevel memories for digital applications.
Proc. IEEE
,
2399 -
2423
-
13)
-
T. Tanzawa
.
A compact on-chip ECC for low cost flash memories.
IEEE J. Solid-State Circuits
,
662 -
669
-
14)
-
L.F. Wei
.
Trellis-coded modulation with multidimensional constellations.
IEEE Trans. Inf. Theory
,
483 -
501
-
15)
-
Lee, S.: `A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology', Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2004, p. 52–513.
-
16)
-
G. Atwood ,
A. Fazio ,
D. Mills ,
B. Reaves
.
(1997)
Intel StrataFlash™ memory technology overview’ Intel Technology Journal.
-
17)
-
H.O. Burton
.
Inversionless decoding of binary BCH codes.
IEEE Trans. Inf. Theory
,
4 ,
464 -
466
-
18)
-
Micheloni, R.: `A 0.13-µm CMOS NOR flash memory experimental chip for 4-b/cell digital storage', Proc. 28th European Solid-State Circuits Conf., September 2002, p. 131–134.
-
19)
-
G. Fettweis ,
H. Meyr
.
High-speed parallel Viterbi decoding: algorithm and VLSI-architecture.
IEEE Commun. Mag.
,
46 -
55
-
20)
-
G. Ungerboeck
.
Trellis-coded modulation with redundant signal sets. Parts I and II.
IEEE Commun. Mag.
,
5 -
21
-
21)
-
J.-D. Lee ,
S.-H. Hur ,
J.-D. Choi
.
Effects of floating-gate interference on NAND flash memory cell operation.
IEEE Trans. Electron Devices
,
264 -
266
-
22)
-
C. Hwang
.
Nanotechnology enables a new memory growth model.
Proc. IEEE
,
1765 -
1771
-
23)
-
K. Takeuchi ,
T. Tanaka ,
H. Nakamura
.
A double-level-Vth select gate array architecture for multilevel NAND flash memories.
IEEE J. Solid-State Circuits
,
602 -
609
-
24)
-
H. Nobukata
.
A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming.
IEEE J. Solid-State Circuits
,
682 -
690
-
25)
-
Micheloni, R.: `A 4 Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36 MB/s system read throughput', IEEE Int. Solid-State Circuits Conf., February 2006, p. 497–506.
-
26)
-
M. Grossi ,
M. Lanzoni ,
B. Ricco
.
A novel algorithm for high-throughput programming of multilevel flash memories.
IEEE Trans. Electron Devices
,
1290 -
1296
-
27)
-
R. Bez ,
E. Camerlenghi ,
A. Modelli ,
A. Visconti
.
Introduction to flash memory.
Proc. IEEE
,
40 ,
489 -
502
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