Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic

Author(s): G. Jaberipur and B. Parhami
DOI: 10.1049/iet-cds:20050228

For access to this article, please select a purchase option:

Buy article PDF

Buy Knowledge Pack

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership

Recommend Title Publication to library

IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Author(s): G. Jaberipur ¹ and B. Parhami ²
- Affiliations: 1: Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
  2: Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Source: Volume 1, Issue 1, February 2007, p. 102 – 110
DOI: 10.1049/iet-cds:20050228 , Print ISSN 1751-858X, Online ISSN 1751-8598

Redundant representations play an important role in high-speed computer arithmetic. One key reason is that such representations support carry-free addition, that is, addition in a small, constant time, independent of operand widths. The implications of stored-transfer representation of digit sets and the associated addition schemes, as an extension of the stored-carry concept to redundant number systems, on the speed and cost of arithmetic algorithms, are explored. Two's-complement digits as the main part and any two-valued digit (twit) in place of a stored carry are allowed, leading to further broadening of the generalised signed-digit representations. The characteristics of the digit sets, possibly not having zero as a member, that allow for most efficient carry-free addition, are investigated. Circuit speed is gained from storing or saving, instead of combining through addition, the interdigit transfers generated during the carry-free addition process. Encoding efficiency is gained from using a twit-transfer set encoded by one logical bit, where more bits would otherwise be needed to represent a transfer value.

References

1. 1)
  - N. Takagi , H. Yasuura , S. Yajima . High-speed VLSI multiplication algorithm with a redundant binary addition tree. IEEE Trans. Comput. , 9 , 789 - 796
2. 2)
  - B. Parhami . Tight upper bonds on the minimum precision required of the divisor and the partial remainder in high-radix division. IEEE Trans. Comput. , 11 , 1509 - 1514
3. 3)
  - D.E. Atkins . An introduction to the role of redundancy in computer arithmetic. Computer , 6 , 74 - 76
4. 4)
  - G. Jaberipur , B. Parhami , M. Ghodsi . Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. IEEE Trans. Circuits Syst. I , 7 , 1348 - 1357
5. 5)
  - B. Parhami . Generalized signed-digit number systems: a unifying framework for redundant number representations. IEEE Trans. Comput. , 1 , 89 - 98
6. 6)
  - H. Edamatsu , T. Taniguchi , T. Nishiyama , S. Kuninobu . A 33 MFLOPS floating point processor using redundant binary representation. Digest of IEEE Int. Conf. on Solid-State Circuits
7. 7)
  - D.W. Matula . Basic digit sets for radix representation. J. ACM , 4 , 1131 - 1143
8. 8)
  - G. Jaberipur , B. Parhami , M. Ghodsi . A class of stored-transfer representations for redundant number systems. Proc. 35th Asilomar Conf. on Signals Systems and Computers , 1304 - 1308
9. 9)
  - M.J. Flynn , S.F. Oberman . (2001) Advanced computer arithmetic design.
10. 10)
  - D.S. Phatak , I. Koren . Constant-time addition and simultaneous format conversion based on redundant binary representations. IEEE Trans. Comput. , 11 , 1267 - 1278
11. 11)
  - D.S. Phatak , I. Koren . Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains. IEEE Trans. Comput. , 880 - 891
12. 12)
  - B. Parhami . (2000) Computer arithmetic: algorithms and hardware designs.
13. 13)
  - A. Avizienis . Signed-digit number representations for fast parallel arithmetic. IRE Trans. Electron. Comput. , 389 - 400
14. 14)
  - P. Kornerup . Digit-set conversions: generalizations and applications. IEEE Trans. Comput. , 5 , 622 - 629
15. 15)
  - G. Jaberipur , M. Ghodsi . High radix signed digit number systems: representation paradigms. Sci. Iranica , 4 , 383 - 391
16. 16)
  - G. Metze , J.E. Robertson . Elimination of carry propagation in digital computers. Proc. Int. Conf. on Information Processing, Paris , 389 - 396
17. 17)
  - W. Balakrishnan , N. Burgess . Very-high-speed VLSI 2s-complement multiplier using signed binary digits. IEE Proc. E, Comput. Digit. Tech. , 29 - 34
18. 18)
  - H. Fahmy , M.J. Flynn . The case for a redundant format in floating-point arithmetic. Proc. 16th IEEE Symp. on Computer Arithmetic , 95 - 102
19. 19)
  - H. Kobayashi . A multioperand two's complement addition algorithm. Proc. 7th IEEE Symp. on Computer Arithmetic , 16 - 19
20. 20)
  - D. Radhakrishnan . Low-voltage low-power CMOS full adder. IEE Proc., Circuits, Devices Syst. , 1 , 19 - 24

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic

Buy article PDF

Buy Knowledge Pack

Thank you

References

Related content