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Design and analysis of digital data recovery circuits using oversampling

Design and analysis of digital data recovery circuits using oversampling

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A performance evaluation and circuit architecture for all-digital data recovery using an oversampling method is proposed. The architecture is very regular and hence very suitable for standard-cell implementation flow. Due to its feedforward architecture, the required bit-rate can be achieved through proper pipelining. These properties make the proposed architecture very suitable as soft silicon intellectual property. Analysis of BER due to the combined effects of the key design parameters like data jitter, clock jitter and oversampling ratio in the oversampling technique are carried out. Thus different specifications of data recovery can be designed with different design parameters. A module generator that can estimate the design parameters automatically is established. Design implementation shows the proposed all-digital data recovery circuit can achieve 3.07 Gbit/s (post-layout) with 0.25 µm 2.5 V CMOS technology standard-cell design and occupies 380×390 µm2 chip area.

References

    1. 1)
    2. 2)
      • `IEEE Draft Standard for a high performance serial bus (supplement)', P1394b Draft 1.3.1, 15 Oct 2001.
    3. 3)
      • R. Ho , K.W. Mai , M. Horowitz . The future of wires. Proc. IEEE , 4 , 490 - 504
    4. 4)
    5. 5)
      • Fiber channel-methodologies for jitter specification, T11.2/Project 1230/Rev 10, June 1999.
    6. 6)
      • Universal Serial Bus specification revision 2.0, Mar 2000.
    7. 7)
      • S. Sidiropoulos , M.A. Horowitz . A semidigital dual delay-locked loop. IEEE J. Solid-State Circuits , 1 , 1683 - 1692
    8. 8)
      • Application Note HFAN-4.5.0 (Rev. 0, 12/00) Maxim integrated products.
    9. 9)
      • A.X. Widmer , P.A. Franaszek . A DC-balanced, partitioned-block, 8B/10B transmission code. IBM J. Res. Develop. , 5 , 440 - 451
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • Jou, S.J., Lin, C.H., Chen, Y.H., Li, Z.H.: `Module generator of data recovery for serial link receiver', Proc. 15th Annual IEEE Int. ASIC/SOC Conf., 2003, p. 49–52.
    14. 14)
    15. 15)
    16. 16)
    17. 17)
      • F.R. Ramin , Ken C.K. Yang , M.A. Horowitz , T.H. Lee . A 0.3-µm CMOS 8-Gbit/s 4 PAM serial link transceiver. IEEE J. Solid-State Circuits , 5 , 757 - 764
    18. 18)
    19. 19)
    20. 20)
      • Jitter specification made easy: a heuristic discussion of fibre channel and gigabit Ethernet methods, Rev 0, Feb 6 2001.
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