Pathak, Jay; Darji, Anand: 'Assessment of interface traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect', IET Circuits, Devices &amp; Systems, 2019, 13, (4), p. 428-434, DOI: 10.1049/iet-cds.2018.5319
IET Digital Library, https://digital-library.theiet.org/;jsessionid=1rw6z7rnub32b.x-iet-live-01content/journals/10.1049/iet-cds.2018.5319