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access icon free Design optimisation procedure for digital mismatch compensation in latch comparators

  • Author(s): Leïla Khanfir 1  and  Jaouhar Mouïne 2
    • View affiliations
  • Source: Volume 12, Issue 6, November 2018, p. 726 – 734
    DOI:  10.1049/iet-cds.2018.5153 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Received 30/04/2018, Accepted 13/09/2018, Revised 29/08/2018, Published 14/09/2018

Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal–oxide–semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.

Inspec keywords: compensation; comparators (circuits); low-power electronics; circuit optimisation; flip-flops; calibration; CMOS logic circuits; logic design; integrated circuit design

Other keywords: digital mismatch compensation; digital calibration schemes; calibration accuracy; complementary metal–oxide–semiconductor technology; high-speed operation; comparator performance; calibration control; post-layout statistical simulations; simple digital sequencer; latch comparator; design optimisation procedure; dynamic comparators; calibration resolution; three-step design procedure; word length 5.9 bit; word length 7.0 bit; size 0.18 mum; reduced power consumption

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Digital circuit design, modelling and testing; Logic design methods; Logic circuits; CMOS integrated circuits; Logic and switching circuits

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