Low supply voltage and multiphase all-digital crystal-less clock generator

Low supply voltage and multiphase all-digital crystal-less clock generator

For access to this article, please select a purchase option:

Buy eFirst article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from  − 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and − 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

Related content

This is a required field
Please enter a valid email address