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DC modelling of SOI four-gate transistor (G4FET) for implementation in circuit simulator using multivariate regression polynomial

DC modelling of SOI four-gate transistor (G4FET) for implementation in circuit simulator using multivariate regression polynomial

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An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G4FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G4FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G4FET circuits.

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