DC modelling of SOI four-gate transistor (G4FET) for implementation in circuit simulator using multivariate regression polynomial

DC modelling of SOI four-gate transistor (G4FET) for implementation in circuit simulator using multivariate regression polynomial

For access to this article, please select a purchase option:

Buy eFirst article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G4FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G4FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G4FET circuits.


    1. 1)
      • 1. Blalock, B.J., Cristoloveanu, S., Dufrene, B.M., et al: ‘The multiple-gate MOS-JFET transistor’, Int. J. High Speed Electron. Syst., 2002, 12, (2), pp. 511520.
    2. 2)
      • 2. Cristoloveanu, S., Blalock, B., Allibert, F., et al: ‘The four-gate transistor’. Proc. of the 2002 European Solid-State Device Research Conf., Firenze, Italy, September 2002, pp. 323326.
    3. 3)
      • 3. Colinge, J.-P.: ‘Silicon- on- insulator technology: materials to VLSI’ (Kluwer, Norwell, MA, USA, 1997, 2nd edn.).
    4. 4)
      • 4. Akarvardar, K., Chen, S., Blalock, B.J., et al: ‘A novel four-quadrant analog multiplier using SOI four-gate transistors (G4-FETs)’. Proc. of ESSCIRC, Grenoble, France, 2005.
    5. 5)
      • 5. Chen, S., Vandersand, J., Blalock, B.J., et al: ‘SOI four-gate transistors (G4-FETs) for high voltage analog applications’. Proc. of ESSCIRC, Grenoble, France, 2005.
    6. 6)
      • 6. Akarvardar, K., Chen, S., Vandersand, J., et al: ‘Four-gate transistor voltage-controlled negative differential resistance device and related circuit applications’. Int. SOI Conf., 2006 IEEE, Niagara Falls, New York, USA, October, 2006, pp. 7172.
    7. 7)
      • 7. Segev, G., Amit, I., Godkin, A., et al: ‘Multiple state electrostatically formed nanowire transistors’, IEEE Electron Device Lett., 2015, 36, (7), pp. 651653.
    8. 8)
      • 8. Friedman, J.S., Godkin, A., Henning, A., et al: ‘Threshold logic with electrostatically formed nanowires’, IEEE Trans. Electron Devices, 2016, 63, (3), pp. 13881391.
    9. 9)
      • 9. Shalev, G., Landman, G., Amit, I., et al: ‘Specific and label-free femtomolar biomarker detection with an electrostatically formed nanowire biosensor’, NPG Asia Mater., 2013, 5, (3), p. e41.
    10. 10)
      • 10. Henning, A., Swaminathan, N., Godkin, A., et al: ‘Tunable diameter electrostatically formed nanowire for high sensitivity gas sensing’, Nano Research, 2015, 8, (7), pp. 22062215.
    11. 11)
      • 11. Terry, S.C., Chen, S., Blalock, B.J., et al: ‘Temperature-compensated reference circuits for SOI’. 2004 IEEE Int. SOI Conf., Charleston, South Carolina, USA, October 2004.
    12. 12)
      • 12. Akarvardar, K., Blalock, B., Chen, S., et al: ‘Digital circuits using SOI four-gate transistor’. Proc. of ICSICT, Shanghai, China, October 2006, pp. 18671869.
    13. 13)
      • 13. Fijany, A., Vatan, F., Mojarradi, M., et al: ‘The G4-FET: a universal and programmable logic gate’. Proc. of the 15th ACM Great Lakes Symp. on VLSI, Chicago, IL, USA, 2005, pp. 349352.
    14. 14)
      • 14. Akarvardar, K., Cristoloveanu, S., Gentil, P., et al: ‘Depletion-all-around operation of the SOI four-gate transistor’, IEEE Trans. Electron Devices, 2007, 54, (2), pp. 323330.
    15. 15)
      • 15. Akarvardar, K., Cristoloveanu, S., Gentil, P.: ‘Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor’, IEEE Trans. Electron Devices, 2006, 53, (10), pp. 25692577.
    16. 16)
      • 16. Dufrene, B., Akarvardar, K., Cristoloveanu, S., et al: ‘Investigation of the four-gate action in G4–FETs’, IEEE Trans. Electron Devices, 2004, 51, (11), pp. 19311935.
    17. 17)
      • 17. Akarvardar, K., Cristoloveanu, S., Bawedin, M., et al: ‘Thin film fully-depleted SOI four-gate transistors’, Solid-State Electron., 2007, 51, (2), pp. 278284.
    18. 18)
      • 18. Sayed, S., Hossain, M.I., Khan, M.Z.R.: ‘A subthreshold swing model for thin-film fully depleted SOI four-gate transistors’, IEEE Trans. Electron Devices, 2012, 59, (3), pp. 854857.
    19. 19)
      • 19. Jiménez Tejada, J.A., Rodríguez, A.L., Godoy, A., et al: ‘Effects of gate oxide and junction nonuniformity on the DC and low-frequency noise performance of four-gate transistors’, IEEE Trans. Electron Devices, 2012, 59, (2), pp. 459467.
    20. 20)
      • 20. Sayed, S., Khan, M.Z.R.: ‘Analytical modeling of surface accumulation behavior of fully depleted SOI four gate transistors (G4-FETs)’, Solid-State Electron., 2013, 81, pp. 105112.
    21. 21)
      • 21. Yanilmaz, M., Eveleigh, V.: ‘Numerical device modeling for electronic circuit simulation’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1991, 10, (3), pp. 366375.
    22. 22)
      • 22. Barby, J.A., Vlach, J., Singhal, K.: ‘Polynomial splines for MOSFET model approximation’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1988, 7, (5), pp. 557566.
    23. 23)
      • 23. Meijer, P.B.: ‘Fast and smooth highly nonlinear multidimensional table models for device modeling’, IEEE Trans. Circuits Syst., 1990, 37, (3), pp. 335346.
    24. 24)
      • 24. Shima, T., Tamada, H., Ryo, L., et al: ‘Table look-up MOSFET modeling system using a 2-D device simulator and monotonic piecewise cubic interpolation’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1983, 2, pp. 721726.
    25. 25)
      • 25. D'Errico, J.: ‘Polyfitn’. MATLAB Central File Exchange. Retrieved 6 August 2015.
    26. 26)
      • 26. Takagi, H., Kano, G.: ‘Complementary JFET negative-resistance devices’, IEEE J. Solid-State Circuits, 1975, 10, (6), pp. 509515.

Related content

This is a required field
Please enter a valid email address