RT Journal Article
A1 Pritha Banerjee
A1 Priyanka Saha
A1 Subir K. Sarkar

PB iet
T1 Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal–oxide–semiconductor field-effect transistor
JN IET Circuits, Devices & Systems
VO 12
IS 5
SP 557
OP 562
AB This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal–oxide–semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the device's immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poisson's equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.
K1 3D Poisson's equation
K1 subthreshold swing
K1 short channel effect
K1 3D analytical model
K1 Si
K1 parabolic potential approximation method
K1 SON
K1 surface potential distribution
K1 threshold-voltage roll-off
K1 gate engineered triple material trigate silicon-on-nothing MOSFET
K1 hot carrier effect
K1 DIBL
K1 three-dimensional analytical model
K1 3D device simulator
K1 ATLAS
K1 SILVACO
K1 metal-oxide-semiconductor field effect transistor
K1 TG
K1 electric field
DO https://doi.org/10.1049/iet-cds.2017.0473
UL https://digital-library.theiet.org/;jsessionid=1ww57gph59m2b.x-iet-live-01content/journals/10.1049/iet-cds.2017.0473
LA English
SN 1751-858X
YR 2018
OL EN