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Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal–oxide–semiconductor field-effect transistor

Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal–oxide–semiconductor field-effect transistor

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This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal–oxide–semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the device's immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poisson's equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.

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