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access icon free Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal–oxide–semiconductor field-effect transistor

This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal–oxide–semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the device's immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poisson's equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.

References

    1. 1)
      • 8. Cartwright, J.: ‘Intel enters the third dimension’, Nature, 2011, doi:10.1038/news.2011.274. Available at http://www.nature.com/news/2011/110506/full/news.2011.274.html, accessed March 2018.
    2. 2)
      • 15. Pal, A., Sarkar, A.: ‘Analytical study of dual-material surrounding gate MOSFET to suppress short channel effects (SCEs)’, Eng. Sci. Technol. Int. J., 2014, 17, pp. 205212.
    3. 3)
      • 13. Deb, S., Singh, N.B., Das, D., et al: ‘Analytical model of threshold voltage and sub-threshold slope of SOI and SON MOSFETs: a comparative study’, J. Electron. Devices, 2010, 8, pp. 300309.
    4. 4)
      • 14. Goel, E., Kumar, S., Singh, K., et al: ‘2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs’, IEEE Trans. Electron. Devices, 2016, 63, (3), pp. 966973.
    5. 5)
      • 12. Young, K.K.: ‘Short-channel effect in fully depleted SOI MOSFETs’, IEEE Trans. Electron. Devices, 1989, 36, (2), pp. 399402.
    6. 6)
      • 4. Rajendran, K., Samudra, G.: ‘A simple modelling of device speed in double-gate SOI MOSFETs’, Microelectron. J., 2000, 31, (4), pp. 255259.
    7. 7)
      • 3. Rechem, D., Latreche, S.: ‘The effect of short channel on nanoscale SOI MOSFETs’, Spec. Issue (Microelectron.) Afr. Phys. Rev., 2008, 2, pp. 8081.
    8. 8)
      • 16. Saha, P., Sarkhel, S., Sarkar, S.K.: ‘Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET’, J. Comput. Electron. Springer, 2017, 16, (3), pp. 648657.
    9. 9)
      • 19. Saramekala, G.K., Santra, A., Kumar, M., et al: ‘Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs’, J. Comput. Electron., 2014, 13, pp. 467476.
    10. 10)
      • 17. Banerjee, P., Sarkar, S.K.: ‘3D analytical modeling of dual material triple gate silicon-on nothing MOSFET’, IEEE Trans. Electron. Devices, 2017, 64, (2), pp. 368375.
    11. 11)
      • 10. Banerjee, P., Sarkar, A., Sarkar, S.K.: ‘Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET’, Microelectron. J., 2017, 67, pp. 5056.
    12. 12)
      • 20. ATLAS User's Manual, SILVACO Int., Santa Clara, CA, USA, 2015.
    13. 13)
      • 5. Naskar, S., Sarkar, S.K.: ‘Quantum analytical model for inversion charge and threshold voltage of short-channel dual-material double-gate SON MOSFET’, IEEE Trans. Electron. Devices, 2013, 60, (9), pp. 27342740.
    14. 14)
      • 1. D'Agostino, F., Quercia, D.: ‘Introduction to VLSI design (EECS 467), short-channel effects in MOSFETs’, 11th December 2000.
    15. 15)
      • 18. Banerjee, P., Sarkar, S.K.: ‘3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects’, J. Comput. Electron., 2017, 16, pp. 631639, doi: 10.1007/s10825-017-1002-y.
    16. 16)
      • 9. Ghanatian, H., Hosseini, S.E.: ‘Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs’, J. Comput. Electron., 2016, 15, (2), pp. 508515.
    17. 17)
      • 11. Reddy, G.V., Kumar, M.J.: ‘A new dual-material double-gate (DMDG) nanoscale SOI MOSFET – two-dimensional analytical modeling and simulation’, IEEE Trans. Electron. Devices, 2005, 4, (2), pp. 260268.
    18. 18)
      • 2. Ajayan, J., Nirmal, D., Prajoon, P., et al: ‘Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications’, Int. J. Electron. Commun., 2017, 79, pp. 151157, doi: http://dx.doi.org/10.1016/j.aeue.2017.06.004.
    19. 19)
      • 6. Goel, K., Saxena, M., Gupta, M., et al: ‘Modeling and simulation of a nanoscale three region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects’, IEEE Trans. Electron. Devices, 2006, 53, (7), pp. 16231633.
    20. 20)
      • 7. Deb, S., Basanta Singh, N., Islam, N., et al: ‘Work function engineering with linearly graded binary metal alloy gate electrode for short-channel SOI MOSFET’, IEEE Trans. Nanotechnol., 2012, 11, (3), pp. 472478.
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