http://iet.metastore.ingenta.com
1887

Downscaling AsTeGeSiN threshold switching devices for high-density 3D memories

Downscaling AsTeGeSiN threshold switching devices for high-density 3D memories

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In high-density three-dimensional (3D) memory technology, a stacking method is used to create memory devices and access devices at the intersections of bit lines and word lines. For this application, access devices should have a high on/off ratio, high current density for writing cycles, and high endurance. Consequently, an arsenic–tellurium–germanium–silicon nitride compound (AsTeGeSiN) threshold switching device with a high current density of 104 A/cm2 above the threshold voltage (V th) is reported as a good candidate for use in access devices. In addition, scaling down of access devices as well as memory devices is essential for high-density 3D memories. However, in AsTeGeSiN threshold switching devices, fast degradation by pulse cycling in smaller devices is observed. To find the main cause of fast degradation by pulse cycling in smaller devices, the low-frequency noise properties are examined. The rapid increase in the trap density (N T) in small devices is the main cause of fast degradation by pulse cycling in AsTeGeSiN devices. On the basis of this evaluation, the author examines the effect of annealing temperature and annealing time on the pulse endurance in smaller devices. Using an annealing temperature of ∼600°C improves the cycling endurance of smaller devices.

References

    1. 1)
      • 1. Cappelletti, P.: ‘Non-volatile memory evolution and revolution’. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, December 2015, pp. 79.
    2. 2)
      • 2. Bourzac, K.: ‘Has Intel created a universal memory technology? [news]’, IEEE Spectr., 2017, 54, (5), pp. 910.
    3. 3)
      • 3. Foong, A., Hady, F.: ‘Storage as fast as rest of the system’. IEEE Int. Memory Workshop, Paris, France, May 2016, pp. 14.
    4. 4)
      • 4. Coughlin, T.: ‘Crossing the chasm to new solid-state storage architectures [The art of storage]’, IEEE Consumer Electron. Mag., 2015, 5, (1), pp. 133142.
    5. 5)
      • 5. Chang, M.-F., Kuo, C.-C., Sheu, S.-S., et al: ‘Area-efficient embedded resistive RAM (ReRAM) macros using logic-process vertical-parasitic-BJT (VPBJT) switches and read-disturb-free temperature-aware current-mode read scheme’, IEEE J. Solid-State Circuits, 2014, 49, (4), pp. 908916.
    6. 6)
      • 6. Kang, W., Zhao, W., Wang, Z., et al: ‘DFSTT-MRAM: dual functional STT-MRAM cell structure for reliability enhancement and 3-D MLC functionality’, IEEE Trans. Magn., 2014, 50, (6), pp. 17.
    7. 7)
      • 7. Liu, T.-y., Yan, T.H., Scheuerlein, R., et al: ‘A 130.7-mm2 2-layer 32-Gb ReRAM memory device in 24-nm technology’, IEEE J. Solid-State Circuits, 2014, 49, (1), pp. 140153.
    8. 8)
      • 8. Chien, W.C., Lee, F.M., Lin, Y.Y., et al: ‘Multi-layer sidewall WOx resistive memory suitable for 3D ReRAM’. Symp. on VLSI Technology, Honolulu, HI, USA, June 2012, pp. 153154.
    9. 9)
      • 9. Chang, M.-F., Chiu, P.-F., Wu, W.-C., et al: ‘Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)’. IEEE Int. Conf. on ASIC, Xiamen, China, October 2011, pp. 14.
    10. 10)
      • 10. Narayanan, P., Burr, G.W., Virwani, K., et al: ‘Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays’, IEEE J. Emerging Sel. Top. Circuits Syst., 2016, 6, (3), pp. 330338.
    11. 11)
      • 11. Lee, M.-J., Lee, D., Kim, H., et al: ‘Highly-scalable threshold switching select device based on chalcogenide glasses for 3D nanoscaled memory arrays’. IEDM Tech. Dig., San Francisco, CA, USA, March 2013, pp. 1013.
    12. 12)
      • 12. Kim, D.: ‘Improved distribution of threshold switching device by reactive nitrogen and plasma treatment’, J. Institute Electron. Inf. Eng., 2014, 51, (8), pp. 18561861.
    13. 13)
      • 13. Ielmini, D., Zhang, Y.: ‘Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices’, J. Appl. Phys., 2007, 102, (5), p. 054517.
    14. 14)
      • 14. Choi, H.-S.: ‘Main degradation mechanism in AsTeGeSiN threshold switching devices’, Microelectron. Reliab., 2016, 56, (1), pp. 6165.
    15. 15)
      • 15. Xie, X., Sarkar, D., Liu, W., et al: ‘Low-frequency noise in bilayer MoS2 transistor’, ACS Nano, 2014, 8, (6), pp. 56335640.
    16. 16)
      • 16. Silva, M.B., Tuinhout, H.P., Duijnhoven, A.Z., et al: ‘A physics-based statistical RTN model for the low frequency noise in MOSFETs’, IEEE Trans. Electron Devices, 2016, 63, (9), pp. 36833692.
    17. 17)
      • 17. Beneventi, G.B., Calderoni, A., Fantini, P., et al: ‘Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices’, J. Appl. Phys., 2009, 106, (5), p. 054506.
    18. 18)
      • 18. Lin, C.-Y., Lee, D.-Y., Wang, S.-Y., et al: ‘Effect of thermal treatment on resistive switching characteristics in Pt/Ti/Al2O3/Pt devices’, Surf. Coat. Technol., 2008, 203, (57), pp. 628631.
    19. 19)
      • 19. Shen, Y.-S., Chiou, B.-S., Ho, C.-C.: ‘Effects of annealing temperature on the resistance switching behaviour of CaCu3Ti4O12 films’, Thin Solid Films, 2008, 517, (3), pp. 12091213.
    20. 20)
      • 20. Shima, H., Akinaga, H.: ‘In-situ nanoscale characterization of annealing effect on TiN/Ti/HfOx/TiN structure for resistive random access memory (ReRAM)’. IEEE Conf. on Nanotechnology, Birmingham, UK, August 2012, pp. 16.
    21. 21)
      • 21. Jin, J.D., Luo, Y., Bao, P., et al: ‘Tuning the electrical properties of ZnO thin-film transistors by thermal annealing in different gases’, Thin Solid Films, 2014, 552, (3), pp. 192195.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0459
Loading

Related content

content/journals/10.1049/iet-cds.2017.0459
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address