Digital LDO modelling techniques for performance estimation at early design stage

Digital LDO modelling techniques for performance estimation at early design stage

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This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.

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