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Bit-parallel systolic multiplier over for irreducible trinomials with ASIC and FPGA implementations

Bit-parallel systolic multiplier over for irreducible trinomials with ASIC and FPGA implementations

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Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over for trinomials. Consequently, an m-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area-delay product, respectively, for m = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.

http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0426
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