16-bit 1-MS/s SAR ADC with foreground digital-domain calibration

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration

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This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and ‘segment error’ of split-CDAC array is proposed. The split-CDAC architecture combines a V cm-free technique in a floating CDAC scheme. The V cm-free technique avoids a power hungry V cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.

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