http://iet.metastore.ingenta.com
1887

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and ‘segment error’ of split-CDAC array is proposed. The split-CDAC architecture combines a V cm-free technique in a floating CDAC scheme. The V cm-free technique avoids a power hungry V cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.

References

    1. 1)
      • 1. Murmann, B.: ‘ADC performance survey 1997-2016’. Available at http://web.stanford.edu/~murmann/adcsurvey.html.
    2. 2)
      • 2. Lee, H.S., Hodges, D.A., Gray, P.R: ‘A self-calibrating 15 bit CMOS A/D converter’, IEEE J. Solid-State Circuits, 1984, SC-19, (6), pp. 813819.
    3. 3)
      • 3. Um, J.Y., Kim, Y.J., Song, E.W., et al: ‘A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits’, IEEE Trans. Circuits Syst. I Reg. Pap., 2013, 60, (11), pp. 28452856.
    4. 4)
      • 4. Liu, W., Huang, P., Chiu, Y.: ‘A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration’. Proc. IEEE CICC, September. 2009, pp. 14.
    5. 5)
      • 5. Morie, T., Miki, T., Matsukawa, K., et al: ‘A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise’. Proc. ISSCC Digest of Technical Papers, February. 2013, pp. 272273.
    6. 6)
      • 6. Harpe, P., Cantatore, E., von Roermund, A.: ‘An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR’. Proc. ISSCC Digest of Technical Papers, February 2014, pp. 194195.
    7. 7)
      • 7. McNeill, J., Coln, M.C.W., Larivee, B.J., et al: ‘‘Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC’, IEEE J. Solid-State Circuits, 2005, 40, (12), pp. 24372445.
    8. 8)
      • 8. Shu, Y.S., Kuo, L.T., Lo, T.Y.: ‘An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS’. Proc. ISSCC Digest of Technical Papers, February. 2016, pp. 458459.
    9. 9)
      • 9. Harpe, P., Zhou, C., Bi, Y., et al: ‘A 26 µW 8 bit 10 MS/s asynchronous SAR ADC for low power energy radios’, IEEE J. Solid-State Circuits, 2011, 46, (7), pp. 15851595.
    10. 10)
      • 10. Tseng, W.-H., Lee, W.-L., Huang, C.-Y., et al: ‘A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for digitally-assisted wireless transmitters’. IEEE A-SSCC Digest of Technical Papers, November. 2015, pp. 14.
    11. 11)
      • 11. Ding, M., Harpe, P., Liu, Y.H., et al: ‘A 46 μw 13 b 6.4 Ms/s SAR ADC with background mismatch and offset calibration’, IEEE J. Solid-State Circuits, 2017, 52, (2), pp. 423432.
    12. 12)
      • 12. Verbruggen, B., Deguchi, K., Malki, B., et al: ‘A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28 nm digital CMOS’. IEEE Symp. VLSI Circuits Digest of Technical Papers, Jun 2014, pp. 12.
    13. 13)
      • 13. Lim, Y., Flynn, M.P.: ‘A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC’, IEEE J. Solid-State Circuits, 2015, 50, (12), pp. 29012911.
    14. 14)
      • 14. Wickmann, A., Ohnhauser, F.: ‘A floating CDAC architecture for high resolution and low-power SAR A/D converter’. Proc. ISCDG, September 2012, pp. 58.
    15. 15)
      • 15. Chen, S.-W.M., Brodersen, R.W.: ‘A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS’, IEEE J. Solid-State Circuits, 2006, 41, (12), pp. 26692680.
    16. 16)
      • 16. Yoshioka, M., Ishikawa, K., Takayama, T., et al: ‘A 10b 50Ms/s 820uW SAR ADC with On-chip digital calibration’. Proc. IEEE ISSCC Digest of Technical Papers, February. 2010, pp. 384385.
    17. 17)
      • 17. Kuttner, F.: ‘A 1.2-V 10-b 20-msample/s nonbinary successive approximation ADC in 0.13-μm CMOS’. Proc. ISSCC Digest of Technical Papers, February. 2002, pp. 176177.
    18. 18)
      • 18. Liu, C.C., Chang, S.J., Huang, G.Y.: ‘A 10b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation’. Proc. ISSCC Digest of Technical Papers, February 2010, pp. 386387.
    19. 19)
      • 19. Srinivasan, C., Godbole, K.M.: ‘Error correction architecture to increase speed and relax current drive requirements of SAR ADC,’ U.S. Patent 6 747 589 B2, July 8, 2004.
    20. 20)
      • 20. Bannon, A., Hurrell, C.P., Hummerston, D., et al: ‘An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range’. Proc. VLSI Circuits Symp. Digest of Technical Papers, June 2014, pp. 12.
    21. 21)
      • 21. Chen, Y., Zhu, X., Tamura, H., et al: ‘Split capacitor DAC mismatch calibration in successive approximation ADC’. Proc. IEEE CICC, September. 2009, pp. 279282.
    22. 22)
      • 22. Ginsburg, B.P., Chandrakasan, A.P.: ‘500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC’, IEEE J. Solid-State Circuits, 2007, 42, (4), pp. 739747.
    23. 23)
      • 23. Abo, A.M., Gray, P.R.: ‘A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter’, IEEE J. Solid-State Circuits, 1999, 34, (5), pp. 599606.
    24. 24)
      • 24. Wang, Y.T., Razavi, B.: ‘An 8-bit 150-MHz CMOS A/D converter’, IEEE J. Solid-State Circuits, 2000, 35, (3), pp. 308317.
    25. 25)
      • 25. Tewksbury, T.L., Lee, H.-S., Miller, G.A., et al: ‘The effects of oxide traps on the large-signal transient response of analog MOS circuits’, IEEE J. Solid-State Circuits, 1989, 24, (2), pp. 542544.
    26. 26)
      • 26. Lu, Y., Fan, C., Sun, L., et al: ‘A fast low power window-opening logic for high speed SAR ADC’, IEICE Electron. Express Lett., 2014, 11, (14), pp. 16.
    27. 27)
      • 27. Harpe, P., Zhou, C., Philips, K., et al: ‘A 0.8-mw 5-bit 250-ms/s time-interleaved asynchronous digital slope ADC’, IEEE J. Solid-State Circuits, 2011, 46, (11), pp. 24502457.
    28. 28)
      • 28. Thirunakkarasu, S., Bakkaloglu, B.: ‘Built-in self-calibration and digital-trim technique for 14-Bit SAR ADCs achieving ± 1 LSB INL’, IEEE Tran. Very Large-Scale Integr. Syst., 2015, 23, (5), pp. 916925.
    29. 29)
      • 29. Shim, M., Jeong, S., Myers, P.D., et al: ‘Edge-pursuit comparator: an energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC’, IEEE J. Solid-State Circuits, 2017, 52, (4), pp. 10771090.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0412
Loading

Related content

content/journals/10.1049/iet-cds.2017.0412
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address