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Design and analysis of a logic model for ultra-low power near threshold adiabatic computing

Design and analysis of a logic model for ultra-low power near threshold adiabatic computing

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The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, temperature, frequency etc. of NTAL circuits have been detailed here. Extensive CADENCE simulations have been done in 22 nm technology node to verify the efficacy of the proposed model. A power clock has been generated based on a switched capacitor regulator to drive the complex NTAL circuits. Analytical and simulated data match with high accuracy which validates the proposed adiabatic logic style in the near threshold regime. A significant amount of energy can be saved by the adiabatic logic with or without considering the power dissipation of the clock generator.

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