RT Journal Article
A1 Sanaz Salem
A1 Hamed Zandevakili
A1 Ali Mahani
A1 Mohsen Saneei

PB iet
T1 Fault-tolerant delay cell for ring oscillator application in 65 nm CMOS technology
JN IET Circuits, Devices & Systems
VO 12
IS 3
SP 233
OP 241
AB A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.
K1 RO
K1 triple transistor redundancy
K1 CMOS technology
K1 SET
K1 Cadence software
K1 single event transient
K1 phased locked loop
K1 quadtransistor redundancy
K1 delayed locked loop
K1 phase noise
K1 power dissipation
K1 fault-tolerant delay celltopology
K1 size 65 nm
K1 clock data recovery
K1 power 34.34 muW
K1 ring oscillator application
K1 reliability
DO https://doi.org/10.1049/iet-cds.2017.0380
UL https://digital-library.theiet.org/;jsessionid=1oru00m25r12t.x-iet-live-01content/journals/10.1049/iet-cds.2017.0380
LA English
SN 1751-858X
YR 2018
OL EN