RT Journal Article
A1 Abdul Majeed K.K.
A1 Binsu J. Kailath

PB iet
T1 PLL architecture with a composite PFD and variable loop filter
JN IET Circuits, Devices & Systems
VO 12
IS 3
SP 256
OP 262
AB A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δ ϕ > π and provides a lower-gain and loop BW during tracking when Δ ϕ < π as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal–oxide–semiconductor process is found to achieve reference spur of −71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of −110 dBc/Hz at 100 kHz and final placement area of 0.244 m m 2 .
K1 time 2.05 mus
K1 time 3.412 ps
K1 voltage-controlled oscillator
K1 frequency 100 kHz
K1 variable loop filter topology
K1 stability
K1 frequency 2.56 GHz
K1 composite PFD
K1 charge pump
K1 phase-locked loop architecture
K1 phase frequency detector
K1 size 180 nm
K1 PLL architecture
K1 phase margin equalization
K1 complementary metal-oxide-semiconductor process
DO https://doi.org/10.1049/iet-cds.2017.0336
UL https://digital-library.theiet.org/;jsessionid=8bfhkdidtbcg.x-iet-live-01content/journals/10.1049/iet-cds.2017.0336
LA English
SN 1751-858X
YR 2018
OL EN