@ARTICLE{ iet:/content/journals/10.1049/iet-cds.2017.0336, author = {Abdul Majeed K.K.}, author = {Binsu J. Kailath}, keywords = {time 2.05 mus;time 3.412 ps;voltage-controlled oscillator;frequency 100 kHz;variable loop filter topology;stability;frequency 2.56 GHz;composite PFD;charge pump;phase-locked loop architecture;phase frequency detector;size 180 nm;PLL architecture;phase margin equalization;complementary metal-oxide-semiconductor process;}, ISSN = {1751-858X}, language = {English}, abstract = {A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δ ϕ > π and provides a lower-gain and loop BW during tracking when Δ ϕ < π as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal–oxide–semiconductor process is found to achieve reference spur of −71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of −110 dBc/Hz at 100 kHz and final placement area of 0.244 m m 2 .}, title = {PLL architecture with a composite PFD and variable loop filter}, journal = {IET Circuits, Devices & Systems}, issue = {3}, volume = {12}, year = {2018}, month = {May}, pages = {256-262(6)}, publisher ={Institution of Engineering and Technology}, copyright = {© The Institution of Engineering and Technology}, url = {https://digital-library.theiet.org/;jsessionid=1l6vrdjqdt5om.x-iet-live-01content/journals/10.1049/iet-cds.2017.0336} }