Efficient digit-serial modular multiplication algorithm on FPGA

Efficient digit-serial modular multiplication algorithm on FPGA

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For cryptographic applications, such as DSA, RSA and ECC systems, the crypto-processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit-serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit-size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit-serial MM architecture requires the latency of clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.

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