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Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network

Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network

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This paper presents reconfigurable and hardware-efficient VLSI architecture of time domain cyclostationary-feature detector (TCD) for spectrum sensing in the cognitive-radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE-Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware-efficient techniques have been introduced for the multiply-&-accumulate and accumulator architectures of suggested TCD design. Real-world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post-layout simulation of the proposed detector have been performed using 65 nm-CMOS technology and it occupies 0.32 mm2 of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state-of-the-art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively

http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0292
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