© The Institution of Engineering and Technology
A novel scheme to design the hardware for error compensation function which self-compensates the truncation error of fixed width multiplier is presented. The proposed method statistically correlates the compensating carries in the truncated part with the carries generated at the truncation boundary in the non-truncated part. The method also utilises the selective dominant carry compensation for controlling the magnitude of error and hardware complexity. The proposed scheme of error compensation in truncated multiplier is investigated for random inputs, Fast Fourier Transform (FFT) application and Finite impulse response (FIR) application. This proposed scheme shows improvement in the major performance parameters such as mean absolute error, mean-square error, maximum error, standard deviation and variance when compared with previously reported schemes. The scheme noticeably decreases the probability of maximum error to 0.22, 0.11 and 0.2 for input scenarios of random, FFT and FIR applications, respectively, which is minimum in comparison to all existing architectures. The scheme is also investigated for the new proposed figure of merit, i.e. energy error product for the truncated multiplier, to select a balanced error and energy optimised truncated multiplier for specific applications.
References
-
-
1)
-
12. Strollo, G.M., Petra, N., De Caro, D.: ‘Dual-tree error compensation for high performance fixed-width multipliers’, IEEE Trans. Circuits Syst. II Express Briefs, 2005, 52, (8), pp. 501–507.
-
2)
-
10. Liao, Y.C., Chang, H.C., Liu, C.W.: ‘Carry estimation for two's complement fixed-width multipliers’. Proc. Workshop Signal Processing Syst., 2006, pp. 345–350.
-
3)
-
8. Van, L., Wang, S., Feng, W.: ‘Design of the lower error fixed-width multiplier and its application’, IEEE Trans. Circuits Syst. II Anal. Digit. Signal Process., 2000, 47, (10), pp. 1112–1118.
-
4)
-
19. Stine, J.E., Duverne, O.M.: ‘Variations on truncated multiplication’. Proc. Euromicro Symp. Digital System Design, 2003.
-
5)
-
23. Garofalo, V.: ‘Truncated binary multiplier with minimum mean square error: analytical characterization circuit implementation and applications’. , 2009, .
-
6)
-
13. Kuang, S.R., Wang, J.P.: ‘Low-error configurable truncated multipliers for multiply-accumulate applications’, Electron. Lett., 2000, 42, (16), pp. 904–905.
-
7)
-
16. Chen, Y.-H., Lu, C.-W., Chiang, H.-C., et al: ‘A low-error statistical fixed-width multiplier and its applications’. Instrumentation & Measurement, Sensor Network and Automation (IMSNA), 2012 Int. Symp., 2012, pp. 39–43.
-
8)
-
11. Park, H., Swartzlander, E.E.Jr.: ‘Truncated multiplication with symmetric correction’. Proc. Asilomar Conf. Signals, Systems, and Computers. (ACSSC), October 2006, pp. 931–934.
-
9)
-
1. Lim, Y.C.: ‘Single precision multiplier with reduced circuit complexity for signal processing applications’, IEEE Trans. Comp., 1992, 41, (10), pp. 1333–1336.
-
10)
-
3. Kidambi, S.S., El-Guibaly, F., Antoniou, A.: ‘Area-efficient multipliers for digital signal processing applications’, IEEE Trans. Circuits Syst. II Exp. Briefs, 1996, 43, (2), pp. 90–95.
-
11)
-
20. De Caro, D., Petra, N., Strollo, A.G.M., et al: ‘Fixed-width multipliers and multipliers-accumulators with min-max approximation error’, IEEE Trans. Circuits Syst. I Reg. Papers, 2013, 60, (9), pp. 2375–2388.
-
12)
-
6. Jou, J.M., Kuang, S.R., Chen, R.D.: ‘Design of low-error fixed-width multipliers for DSP applications’, IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., 1999, 46, (6), pp. 836–842.
-
13)
-
5. Swartzlander, E.E.Jr.: ‘Truncated multiplication with approximate rounding’. Proc. 33th Asilomar Conf. Signals, Circuits System, 1999, pp. 1480–1483.
-
14)
-
7. Jou, S.J., Wang, H.H.: ‘Fixed-width multiplier for DSP application’. Proc. IEEE Int. Symp. Computer Design, 2000, pp. 318–332.
-
15)
-
14. Petra, N., Caro, D.D., Garofalo, V., et al: ‘Truncated binary multipliers with variable correction and minimum mean square error’, IEEE Trans. Circuits Syst. I Reg. Papers, 2010, 57, (6), pp. 1312–1325.
-
16)
-
17)
-
21. Wey, I.-C., Peng, C.-C., Liao, F.-Y.: ‘Reliable low-power multiplier design using fixed width replica redundancy block’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2015, 23, (1), pp. 78–87.
-
18)
-
2. Shulte, M.J., Swartzlander, E.E.Jr.: ‘Truncated multiplication with correction constant’. VLSI Signal Processing VI, 1993, pp. 388–396.
-
19)
-
15. Wey, I.-C., Wang, C.C.: ‘Low-error and hardware-efficient fixed width multiplier by using the dual-group minor input correction vector to lower input correction vector compensation error’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (10), pp. 1923–1928.
-
20)
-
18. Juang, T.-B., Hsiao, S.-F.: ‘Low-error carry-free fixed-width multipliers with low-cost compensation circuits’, IEEE Trans. Circuits Syst. II, 2005, 52, (6), pp. 299–303.
-
21)
-
4. King, E.J., Swartzlander, E.E.Jr.: ‘Data dependent truncated scheme for parallel multiplication’. Proc. 31th Asilomar Conf. Signals, Circuits System, 1997, pp. 1178–1182.
-
22)
-
22. Baugh, E.C.R., Wooley, B.A.: ‘A two's complement parallel array multiplication algorithm’, IEEE Trans. Comput., 1973, C-22, (12), pp. 1045–1047.
-
23)
-
17. Joshi, P., Deshmukh, R.B., Pandey, K., et al: ‘A novel combined approach of constant correction and variable correction method to minimize the mean square error and compensation hardware for fixed width multiplier design’. Electronics, Computing and Communication Technologies (CONECCT), 2015 IEEE Int. Conf., 10–11 July 2015.
-
24)
-
9. Van, L.-D., Yang, C.-C.: ‘Generalized low-error area-efficient fixedwidth multipliers’, IEEE Trans. Circuits Syst. I Reg. Papers, 2005, 52, (8), pp. 1608–1619.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0136
Related content
content/journals/10.1049/iet-cds.2017.0136
pub_keyword,iet_inspecKeyword,pub_concept
6
6