http://iet.metastore.ingenta.com
1887

Analytical modelling of work-function modulated delta-doped TFET to improve analogue performance

Analytical modelling of work-function modulated delta-doped TFET to improve analogue performance

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this study, an analytical model for linearly modulated work-function-based delta-doped single-gate tunnel field-effect transistor (TFET) has been developed to improve the analogue performance. The impact of delta-doped layer and linearly modulated metal gate on different analogue parameters has been investigated extensively. The insertion of heavily doped delta layer in the source region improves ON current and current switching ratio performance significantly as compared to conventional TFET. Similarly, the presence of spatially work-function modulated metal gate reduces subthreshold swing and improves performance. The distance of the delta layer from the source–channel interface is optimised to 3 nm to maximise efficiency. The proposed model exhibits much improved analogue performance as compared to conventional TFET and delta-doped TFET. Thus, the model can be viewed as one of the potential replacements for metal–oxide–semiconductor field-effect transistors in ultra-low-power applications. However, the precision of present model is corroborated by using the two-dimensional TCAD Sentaurus simulator.

References

    1. 1)
      • 1. Datta, S., Liu, H., Narayanan, V.: ‘Tunnel FET technology: a reliability perspective’, Solid State Electron., 2014, 54, pp. 861874.
    2. 2)
      • 2. Vijayvargiya, V., Vishvakarma, S.K.: ‘Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance’, IEEE Trans. Nanotechnol., 2014, 13, pp. 974981.
    3. 3)
      • 3. Zhang, Q., Zhao, W., Seabaugh, A.: ‘Low subthreshold-swing tunnel transistors’, IEEE Electron Device Lett., 2006, 27, pp. 297300.
    4. 4)
      • 4. Choi, W.Y., Park, B.G., Lee, J.D., et al: ‘Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec’, IEEE Electron Device Lett., 2007, 28, pp. 743745.
    5. 5)
      • 5. Chowdhury, N., Ahmed, I., Fakhrul, T., et al: ‘A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications’, Physica E, 2015, 74, pp. 251257.
    6. 6)
      • 6. Samuel, T.S.A., Balamurugan, N.B., Bhuvaneswari, S., et al: ‘Analytical modelling and simulation of single-gate SOI TFET for low-power applications’, Int. J. Electron., 2014, 101, pp. 779788.
    7. 7)
      • 7. Vandenberghe, W.G., Verhulst, A.S., Groeseneken, G., et al: ‘Analytical model for a tunnel field-effect transistor’. Proc. of IEEE Mediterranean Conf. on Electro-technical Conf., Ajaccio, 2008, pp. 923928.
    8. 8)
      • 8. Lee, M.J., Choi, W.Y.: ‘Analytical model of single-gate silicon-on- insulator (SOI) tunneling field-effect transistors (TFETs)’, Solid-State Electron., 2011, 63, pp. 110114.
    9. 9)
      • 9. Kanungo, S., Rahaman, H., Dasgupta, P.S.: ‘A simple analytical model of silicon on insulator tunnel FET’. Proc. of IEEE Int. Conf. on Computers and Devices for Communication, Kolkata, 2012, pp. 14.
    10. 10)
      • 10. Kumari, P., Dash, S., Mishra, G.P.: ‘Impact of technology scaling on analog and RF performance of SOI–TFET’, Adv. Nat. Sci., Nanosci. Nanotechnol., 2015, 6, pp. 045005-1045005-10.
    11. 11)
      • 11. Zhang, L., Lin, X., He, J., et al: ‘An analytical charge model for double-gate tunnel FETs’, IEEE Trans. Electron Devices, 2012, 59, pp. 32173223.
    12. 12)
      • 12. Wu, C., Huang, R., Huang, Q., et al: ‘An analytical surface potential model accounting for the dual- modulation effects in tunnel FETs’, IEEE Trans. Electron Devices, 2014, 61, pp. 26902696.
    13. 13)
      • 13. Dash, S., Mishra, G.P.: ‘A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance’, Adv. Nat. Sci., Nanosci. Nanotechnol., 2015, 6, pp. 035005-1035005-10.
    14. 14)
      • 14. Patel, N., Ramesha, A., Mahapatra, S.: ‘Drive current boosting of n-type tunnel FET with strained SiGe layer at source’, Microelectron. J., 2008, 39, pp. 16711677.
    15. 15)
      • 15. Anghel, C., Chilagani, P., Amara, A., et al: ‘Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric’, Appl. Phys. Lett., 2010, 96, pp. 122104-1122104-3.
    16. 16)
      • 16. Gholizadeh, M., Hosseini, S.E.: ‘A 2-D analytical model for double-gate tunnel FETs’, IEEE Trans. Electron Devices, 2014, 61, pp. 14941500.
    17. 17)
      • 17. Dash, S., Mishra, G.P.: ‘A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET)’, Superlattices Microstruct., 2015, 86, pp. 211220.
    18. 18)
      • 18. Boucart, K., Ionescu, A.M.: ‘Double-gate tunnel FET with high-κ gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, pp. 17251733.
    19. 19)
      • 19. Choi, W.Y., Lee, W.: ‘Hetero-gate-dielectric tunneling field effect transistors’, IEEE Trans. Electron Devices, 2010, 57, pp. 23172319.
    20. 20)
      • 20. Kim, S.H., Agarwal, S., Jacobson, Z.A., et al: ‘Tunnel field effect transistors with raised germanium source’, IEEE Electron Devices Lett., 2010, 31, pp. 11071109.
    21. 21)
      • 21. Chang, H., Adams, B., Chien, P., et al: ‘Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing’, IEEE Trans. Electron Devices, 2013, 60, pp. 9296.
    22. 22)
      • 22. Huang, Q., Huang, R., Zhan, Z., et al: ‘Performance improvement of Si pocket-tunnel FET with steep subthreshold slope and high ION/IOFF ratio’. Proc. of IEEE Int. Conf. on Solid-State and Integrated Circuit Technology, Xi'an, 2012, pp. 13.
    23. 23)
      • 23. Dash, S., Jena, B., Mishra, G.P.: ‘A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping’, Superlattices Microstruct., 2016, 97, pp. 231241.
    24. 24)
      • 24. Panda, S., Dash, S., Behera, S.K., et al: ‘Delta-doped tunnel FET (D-TFET) to improve current ratio (ION/IOFF) and ON-current performance’, J. Comput. Electron., 2016, 15, pp. 857864.
    25. 25)
      • 25. Ganapathi, K., Salahuddin, S.: ‘Heterojunction vertical band-to-band tunneling transistors for steep subthreshold swing and high ON current’, IEEE Electron Devices Lett., 2011, 32, pp. 689691.
    26. 26)
      • 26. Virani, H.G., Kottantharayil, A.: ‘Optimization of hetero junction n-channel tunnel FET with high-k spacers’. Proc. of IEEE Int. Workshop on Electron Devices and Semiconductor Technology, Mumbai, 2009, pp. 16.
    27. 27)
      • 27. Schubert, E.F.: ‘Delta doping of III-V compound semiconductors: fundamentals and device applications’, J. Vac. Sci. Technol. A, 1990, 8, pp. 29802996.
    28. 28)
      • 28. Sciana, B., Radziewicz, D., Paszkiewicz, B., et al: ‘MOVPE technology and characterisation of silicon δ-doped GaAs and AlxGa1-xAs’, Thin Solid Films, 2002, 412, pp. 5559.
    29. 29)
      • 29. Kim, P., Lee, K.M., Lee, E.W., et al: ‘A delta-doped amorphous silicon thin-film transistor with high mobility and stability’, J. Korean Phys. Soc., 2012, 61, pp. 18351839.
    30. 30)
      • 30. Dash, S., Sahoo, G.S., Mishra, G.P.: ‘Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate’, Superlattices Microstruct., 2016, 91, pp. 105111.
    31. 31)
      • 31. Manna, B., Sarkhel, S., Islam, N., et al: ‘Spatial composition grading of binary metal alloy gate electrode for short-channel SOI/SON MOSFET application’, IEEE Trans. Electron Devices, 2012, 59, pp. 32803287.
    32. 32)
      • 32. Sarkhel, S., Sarkar, S.K.: ‘A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance’, J. Comput. Electron., 2014, 13, pp. 925932.
    33. 33)
      • 33. Sarkhel, S., Bagga, N., Sarkar, S.K.: ‘Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor’, J. Comput. Electron., 2015, 15, pp. 104114.
    34. 34)
      • 34. Choi, K.M., Choi, W.Y.: ‘Work-Function variation effects of tunneling field-effect transistors (TFETs)’, IEEE Electron Devices Lett., 2013, 34, pp. 942944.
    35. 35)
      • 35. Li, T.-L., Hu, C.-H., Ho, W.-L., et al: ‘Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf–Mo binary alloys’, IEEE Trans. Electron Devices, 2005, 52, pp. 11721179.
    36. 36)
      • 36. Pan, A., Liu, R., Sun, M., et al: ‘Spatial composition grading of quaternary ZnCdSSe alloy nanowires with tunable light emission between 350 and 710 nm on a single substrate’, ACS Nano, 2010, 4, pp. 671680.
    37. 37)
      • 37. Sentaurus device user guide’ (Synopsys, Inc., Mountain View, 2010).
    38. 38)
      • 38. Vishnoi, R., Jagadesh Kumar, M.: ‘2-D analytical model for the threshold voltage of a tunneling FET with localized charges’, IEEE Trans. Electron Devices, 2014, 61, pp. 30543059.
    39. 39)
      • 39. Vandenberghe, W.G., Verhulst, A.S., Soree, B., et al: ‘Figure of merit for and identification of sub-60 mV/decade devices’, Appl. Phys. Lett., 2013, 102, pp. 013510-1013510-4.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0135
Loading

Related content

content/journals/10.1049/iet-cds.2017.0135
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address