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1887

access icon free Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

© The Institution of Engineering and Technology
Received 20/03/2017, Accepted 27/01/2018, Revised 19/12/2017, Published 31/01/2018

This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

Inspec keywords: evolutionary computation; operational amplifiers; CMOS analogue integrated circuits; differential amplifiers; integrated circuit layout; optimisation; telecommunication network routing

Other keywords: evolutionary algorithm; three-stage operational amplifier; Placement and routing method; layout parasitic effect; analogue layout generation; analogue integrated circuit layout generation; two-stage operational amplifier; size 0.18 mum; op-amps; CMOS process; voltage 1.8 V; differential to single-ended amplification stage; modified cuckoo optimisation algorithm

Subjects: Amplifiers; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Optimisation techniques

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