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Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

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This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

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