access icon free Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications

© The Institution of Engineering and Technology
Received 29/03/2017, Accepted 17/05/2017, Published 26/05/2017

This study presents an efficient and high-speed very large-scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2 m ) with Gaussian normal basis representation. The proposed implementation is a low-cost structure constructed by one digit-serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low-cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

Inspec keywords: integrated circuit design; application specific integrated circuits; very high speed integrated circuits; Galois fields; scheduling; public key cryptography; CMOS integrated circuits

Other keywords: transistors; field multiplier structure; digit-serial multiplier; logical effort technique; high-speed very large-scale integration implementation; full-custom hardware implementation; point multiplication architecture; size 0.18 mum; low-cost structure; binary Edwards curves; point multiplication scheduling; point doubling computations; point addition computations; binary finite field GF(2m); Gaussian normal basis representation; point multiplication circuit; application-specific integrated circuit elliptic curve cryptosystem applications; CMOS technology

Subjects: Cryptography; CMOS integrated circuits; Codes; Semiconductor integrated circuit design, layout, modelling and testing

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