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11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal–oxide–semiconductor

11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal–oxide–semiconductor

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In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energy-efficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal–oxide–semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step.

http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2017.0029
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