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access icon free Course on secure hardware design of silicon chips

  • Author(s): Basel Halak 1, 2
    • View affiliations
  • Source: Volume 11, Issue 4, July 2017, p. 304 – 309
    DOI:  10.1049/iet-cds.2017.0028 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Received 20/01/2017, Accepted 24/02/2017, Published 28/02/2017

This study describes the design and evaluation of a secure chip design module for graduate students and junior engineers with electronics and computer engineering. This course has two broad goals, the first is to teach students how design complex systems on chips using industry standard tools and the second is to educate them on emerging hardware security threats and countermeasures. There are a number of strategies currently been employed to handle the rising complexity of chip design, namely reuse, abstraction and automation. The authors aim to show how to employ these approaches to produce working systems within a time-constrained environment similar to that of IC design companies. One of the unique features of this module is its approach of treating hardware security as an integral part of the chip design process and as one of the design metrics which can be evaluated and optimised, this allows students to better understand the root causes of this issue and to think more constructively about potential countermeasures. The course is designed based on the principles of constructive alignment method and Kolb learning cycle. Detailed syllabus and assessment exercises are included. Feedback results from students' surveys indicate that the module has been positively received.

Inspec keywords: circuit complexity; electronic design automation; system-on-chip; electronic engineering education; educational courses; security of data; further education; teaching; integrated circuit design

Other keywords: complex systems on chip design teaching; secure chip design module evaluation; secure hardware design course; chip design complexity handling; industry standard tools; constructive alignment method; assessment exercises; silicon chips; Kolb learning cycle; graduate students; junior engineers; hardware security countermeasures; electronics and computer engineering; hardware security threats; syllabus

Subjects: System-on-chip; Computational complexity; Electronic engineering computing; System-on-chip; Digital circuit design, modelling and testing; Education and training

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