access icon free Six-bit, reusable comparator stage-based asynchronous binary-search SAR ADC using smart switching network

A reusable comparator stage-based asynchronous binary-search Successive Approximation Register (SAR) analogue-to-digital converter (ADC) with a smart reference range prediction network is presented in this brief. The proposed architecture has an advantageous merit of using only N comparators in comparison with original binary-search ADC and flash ADC. The design uses selection logic which selects and activates the comparator one at a time, and a smart switching network which allocates reference voltage to selected comparators in the successive comparison process. It claims for equipoise with power and operating speed when compared with flash ADC and SAR ADC. The post-layout simulated performance of 6 bit conversion using only six comparators on United Microelectronics Corporation (UMC)-180 nm achieves 41 dB spurious-free dynamic range and 36.02 dB signal-to-noise distortion ratio with a maximum sampling speed of 330 MS/s consuming 0.64 mW power when operated at 1.8 V supply, corresponding figure-of-merit 36.47 fJ/conversion step.

Inspec keywords: analogue-digital conversion; comparators (circuits)

Other keywords: reusable comparator stage; selection logic; UMC; successive comparison process; signal-to-noise distortion ratio; voltage 1.8 V; figure-of-merit; analogue-to-digital converter; power 0.64 mW; spurious-free dynamic range; reference voltage; smart switching network; operating speed; flash ADC; post-layout simulated performance; asynchronous binary-search SAR ADC; word length 6 bit; smart reference range prediction network

Subjects: A/D and D/A convertors; A/D and D/A convertors

References

    1. 1)
      • 6. Louwsma, S., Van Tuijl, A., Vertregt, M., et al: ‘A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 µm CMOS’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 778786.
    2. 2)
      • 22. Wenyan, X., Qi, W., Li, L., et al: ‘A 6-bit 320-MS/s 2-bit/cycle SAR ADC with tri-level charge redistribution’. IEEE Int. Conf. Anti-Counterfeiting, Security, and Identification (ASID), September 2015, pp. 7175.
    3. 3)
      • 15. Zhang, L., Li, D., Zhu, Z., et al: ‘An 8 bit 500 MS/s asynchronous single-channel SAR ADC in 65 nm CMOS’, Analog Integr. Circuits Signal Process., 2015, 83, (1), pp. 103109.
    4. 4)
      • 3. Zhu, Z., Liu, M., Wang, Q., et al: ‘A single-channel 8 bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS’, Microelectron. J., 2014, 45, (7), pp. 880885.
    5. 5)
      • 4. Benjamin, R., German, P., Raúl, S., et al: ‘A 2GS/s 6 bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques’, Analog Integr. Circuits Signal Process., 2015, 85, (1), pp. 316.
    6. 6)
      • 5. Ginsburg, B., Chandrakasan, A.: ‘Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver’, IEEE J. Solid-State Circuits, 2007, 42, (2), pp. 247257.
    7. 7)
      • 9. Wong, Y., Cohen, M., Abshire, P.: ‘A 750 MHz 6 b adaptive floating-gate quantizer in 0.35 µm CMOS’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2009, 56, (7), pp. 13011312.
    8. 8)
      • 20. Nikandish, G., Medi, A.: ‘Analysis of integral non-linearity errors in two-step analogue-to-digital converters’, IET Circuits Devices Syst.., 2012, 6, (1), pp. 18.
    9. 9)
      • 26. Xue, H., Qi, W., Huazhong, Y., et al: ‘A single channel, 6 bit 230 MS/s asynchronous SAR ADC based on 2 bits/stage’, J. Semicond., 2014, 35, (7), p. 075005(1–6).
    10. 10)
      • 10. Wang, Z., Chang, M.: ‘A 1 V 1.25 GS/s 8 bit self-calibrated flash ADC in 90 nm digital CMOS’, IEEE Trans. Circuits Syst. II, Express Briefs, 2008, 55, (7), pp. 668672.
    11. 11)
      • 13. Liu, S., Shen, Y., Zhu, Z.: ‘A 12 bit 10 MS/s SAR ADC with high linearity and energy-efficient switching’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2016, 63, (10), pp. 16161627.
    12. 12)
      • 8. Wang, Z., Chang, M.: ‘A 600-MSPS 8 bit CMOS ADC using distributed track-and-hold with complementary resistor/capacitor averaging’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2008, 55, (11), pp. 36213627.
    13. 13)
      • 11. Guanzhong, H., Pingfen, L.: ‘1.1 V, 8 bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-to-digital converter in 0.18 μm CMOS with separated capacitor arrays’, IET Circuits Devices Syst.., 2013, 7, (1), pp. 18.
    14. 14)
      • 1. He, Lin, Jiaqi, Y., Duona, L., et al: ‘A speed-enhancing dual-trail instantaneous switching architecture for SAR ADCs’, IEEE Trans. Circuits Syst. II, Express Briefs, 2015, 62, (1), pp. 2630.
    15. 15)
      • 12. El-Chammas, M., Murmann, B.: ‘A 12 GS/s 81 mW 5 bit time-interleaved flash ADC with background timing skew calibration’, IEEE J. Solid-State Circuits, 2011, 46, (4), pp. 838847.
    16. 16)
      • 23. Tai, H.-Y., Tsai, C.-H., Tsai, P.-Y., et al: ‘A 6 bit 1 GS/s two-step SAR ADC in 40 nm CMOS’, IEEE Trans. Circuits Syst. II, Express Briefs, 2014, 61, (5), pp. 339343.
    17. 17)
      • 2. Jiang, T., Wing, L., Freeman, Y., et al: ‘A single-channel, 1.25 GS/s, 6 bit, 6.08 mW asynchronous successive-approximation ADC with improved feedback delay in 40 nm CMOS’, IEEE J. Solid-State Circuits, 2012, 47, (10), pp. 24442453.
    18. 18)
      • 24. Xue, H., Qi, W., Huazhong, Y., et al: ‘A single channel, 6 bit 410 MS/s 3 bits/stage asynchronous SAR ADC based on resistive DAC’, J. Semicond., 2015, 36, (5), p. 055010(1–7).
    19. 19)
      • 17. Wong, S., Chio, U., Chan, C., et al: ‘A 4.8 bit ENOB 5 bit 500 MS/s binary-search ADC with minimized number of comparators’. IEEE Asian Solid-State Circuits Conf., Jeju, Korea, November 2011, pp. 7376.
    20. 20)
      • 18. Jeon, H., Kim, Y.: ‘A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator’, Analog Integr. Circuits Signal Process., 2012, 70, (3), pp. 337346.
    21. 21)
      • 14. Zhu, Z., Liang, Y.: ‘A 0.6 V 38 nW 9.4-ENOB 20 kS/s SAR ADC in 0.18 µm-CMOS for medical implant devices’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (9), pp. 21672176.
    22. 22)
      • 25. Jixuan, X., Chixiao, C., Fan, Y., et al: ‘A 6 b 600 MS/s SAR ADC with a new switching procedure of 2 b/stage and self-locking comparators’, J. Semicond., 2015, 36, (5), p. 055009(1–7).
    23. 23)
      • 19. Lei, Q., Yuanjin, Z., Liter, S.: ‘Source follower-based high-speed switched capacitor amplifier for pipelined ADCs’, IET Electron. Lett., 2015, 51, (1), pp. 2123.
    24. 24)
      • 7. Lin, Y., Chang, S., Liu, Y., et al: ‘An asynchronous binary-search ADC architecture with a reduced comparator count’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2010, 57, (8), pp. 18291836.
    25. 25)
      • 21. Zhangming, Z., Zheng, Q., Maliang, L., et al: ‘A 6-to-10 Bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 µm CMOS’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (3), pp. 689696.
    26. 26)
      • 16. Van der Plas, G., Verbruggen, B.: ‘A 150 MS/s 133 µW 7 b ADC in 90 nm digital CMOS using a comparator-based asynchronous binary search sub-ADC’. IEEE Int. Solid-State Circuits Conf. (ISSCC Digest Technical Papers), February 2008, pp. 242243.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0499
Loading

Related content

content/journals/10.1049/iet-cds.2016.0499
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading