http://iet.metastore.ingenta.com
1887

Six-bit, reusable comparator stage-based asynchronous binary-search SAR ADC using smart switching network

Six-bit, reusable comparator stage-based asynchronous binary-search SAR ADC using smart switching network

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A reusable comparator stage-based asynchronous binary-search Successive Approximation Register (SAR) analogue-to-digital converter (ADC) with a smart reference range prediction network is presented in this brief. The proposed architecture has an advantageous merit of using only N comparators in comparison with original binary-search ADC and flash ADC. The design uses selection logic which selects and activates the comparator one at a time, and a smart switching network which allocates reference voltage to selected comparators in the successive comparison process. It claims for equipoise with power and operating speed when compared with flash ADC and SAR ADC. The post-layout simulated performance of 6 bit conversion using only six comparators on United Microelectronics Corporation (UMC)-180 nm achieves 41 dB spurious-free dynamic range and 36.02 dB signal-to-noise distortion ratio with a maximum sampling speed of 330 MS/s consuming 0.64 mW power when operated at 1.8 V supply, corresponding figure-of-merit 36.47 fJ/conversion step.

References

    1. 1)
      • Lin He , Y. Jiaqi , L. Duona .
        1. He, Lin, Jiaqi, Y., Duona, L., et al: ‘A speed-enhancing dual-trail instantaneous switching architecture for SAR ADCs’, IEEE Trans. Circuits Syst. II, Express Briefs, 2015, 62, (1), pp. 2630.
        . IEEE Trans. Circuits Syst. II, Express Briefs , 1 , 26 - 30
    2. 2)
      • T. Jiang , L. Wing , Y. Freeman .
        2. Jiang, T., Wing, L., Freeman, Y., et al: ‘A single-channel, 1.25 GS/s, 6 bit, 6.08 mW asynchronous successive-approximation ADC with improved feedback delay in 40 nm CMOS’, IEEE J. Solid-State Circuits, 2012, 47, (10), pp. 24442453.
        . IEEE J. Solid-State Circuits , 10 , 2444 - 2453
    3. 3)
      • Z. Zhu , M. Liu , Q. Wang .
        3. Zhu, Z., Liu, M., Wang, Q., et al: ‘A single-channel 8 bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS’, Microelectron. J., 2014, 45, (7), pp. 880885.
        . Microelectron. J. , 7 , 880 - 885
    4. 4)
      • R. Benjamin , P. German , S. Raúl .
        4. Benjamin, R., German, P., Raúl, S., et al: ‘A 2GS/s 6 bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques’, Analog Integr. Circuits Signal Process., 2015, 85, (1), pp. 316.
        . Analog Integr. Circuits Signal Process. , 1 , 3 - 16
    5. 5)
      • B. Ginsburg , A. Chandrakasan .
        5. Ginsburg, B., Chandrakasan, A.: ‘Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver’, IEEE J. Solid-State Circuits, 2007, 42, (2), pp. 247257.
        . IEEE J. Solid-State Circuits , 2 , 247 - 257
    6. 6)
      • S. Louwsma , A. Van Tuijl , M. Vertregt .
        6. Louwsma, S., Van Tuijl, A., Vertregt, M., et al: ‘A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 µm CMOS’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 778786.
        . IEEE J. Solid-State Circuits , 4 , 778 - 786
    7. 7)
      • Y. Lin , S. Chang , Y. Liu .
        7. Lin, Y., Chang, S., Liu, Y., et al: ‘An asynchronous binary-search ADC architecture with a reduced comparator count’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2010, 57, (8), pp. 18291836.
        . IEEE Trans. Circuits Syst. I, Regul. Pap. , 8 , 1829 - 1836
    8. 8)
      • Z. Wang , M. Chang .
        8. Wang, Z., Chang, M.: ‘A 600-MSPS 8 bit CMOS ADC using distributed track-and-hold with complementary resistor/capacitor averaging’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2008, 55, (11), pp. 36213627.
        . IEEE Trans. Circuits Syst. I, Regul. Pap. , 11 , 3621 - 3627
    9. 9)
      • Y. Wong , M. Cohen , P. Abshire .
        9. Wong, Y., Cohen, M., Abshire, P.: ‘A 750 MHz 6 b adaptive floating-gate quantizer in 0.35 µm CMOS’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2009, 56, (7), pp. 13011312.
        . IEEE Trans. Circuits Syst. I, Regul. Pap. , 7 , 1301 - 1312
    10. 10)
      • Z. Wang , M. Chang .
        10. Wang, Z., Chang, M.: ‘A 1 V 1.25 GS/s 8 bit self-calibrated flash ADC in 90 nm digital CMOS’, IEEE Trans. Circuits Syst. II, Express Briefs, 2008, 55, (7), pp. 668672.
        . IEEE Trans. Circuits Syst. II, Express Briefs , 7 , 668 - 672
    11. 11)
      • H. Guanzhong , L. Pingfen .
        11. Guanzhong, H., Pingfen, L.: ‘1.1 V, 8 bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-to-digital converter in 0.18 μm CMOS with separated capacitor arrays’, IET Circuits Devices Syst.., 2013, 7, (1), pp. 18.
        . IET Circuits Devices Syst.. , 1 , 1 - 8
    12. 12)
      • M. El-Chammas , B. Murmann .
        12. El-Chammas, M., Murmann, B.: ‘A 12 GS/s 81 mW 5 bit time-interleaved flash ADC with background timing skew calibration’, IEEE J. Solid-State Circuits, 2011, 46, (4), pp. 838847.
        . IEEE J. Solid-State Circuits , 4 , 838 - 847
    13. 13)
      • S. Liu , Y. Shen , Z. Zhu .
        13. Liu, S., Shen, Y., Zhu, Z.: ‘A 12 bit 10 MS/s SAR ADC with high linearity and energy-efficient switching’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2016, 63, (10), pp. 16161627.
        . IEEE Trans. Circuits Syst. I, Regul. Pap. , 10 , 1616 - 1627
    14. 14)
      • Z. Zhu , Y. Liang .
        14. Zhu, Z., Liang, Y.: ‘A 0.6 V 38 nW 9.4-ENOB 20 kS/s SAR ADC in 0.18 µm-CMOS for medical implant devices’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (9), pp. 21672176.
        . IEEE Trans. Circuits Syst. I, Regul. Pap. , 9 , 2167 - 2176
    15. 15)
      • L. Zhang , D. Li , Z. Zhu .
        15. Zhang, L., Li, D., Zhu, Z., et al: ‘An 8 bit 500 MS/s asynchronous single-channel SAR ADC in 65 nm CMOS’, Analog Integr. Circuits Signal Process., 2015, 83, (1), pp. 103109.
        . Analog Integr. Circuits Signal Process. , 1 , 103 - 109
    16. 16)
      • G. Van der Plas , B. Verbruggen .
        16. Van der Plas, G., Verbruggen, B.: ‘A 150 MS/s 133 µW 7 b ADC in 90 nm digital CMOS using a comparator-based asynchronous binary search sub-ADC’. IEEE Int. Solid-State Circuits Conf. (ISSCC Digest Technical Papers), February 2008, pp. 242243.
        . IEEE Int. Solid-State Circuits Conf. (ISSCC Digest Technical Papers) , 242 - 243
    17. 17)
      • S. Wong , U. Chio , C. Chan .
        17. Wong, S., Chio, U., Chan, C., et al: ‘A 4.8 bit ENOB 5 bit 500 MS/s binary-search ADC with minimized number of comparators’. IEEE Asian Solid-State Circuits Conf., Jeju, Korea, November 2011, pp. 7376.
        . IEEE Asian Solid-State Circuits Conf. , 73 - 76
    18. 18)
      • H. Jeon , Y. Kim .
        18. Jeon, H., Kim, Y.: ‘A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator’, Analog Integr. Circuits Signal Process., 2012, 70, (3), pp. 337346.
        . Analog Integr. Circuits Signal Process. , 3 , 337 - 346
    19. 19)
      • Q. Lei , Z. Yuanjin , S. Liter .
        19. Lei, Q., Yuanjin, Z., Liter, S.: ‘Source follower-based high-speed switched capacitor amplifier for pipelined ADCs’, IET Electron. Lett., 2015, 51, (1), pp. 2123.
        . IET Electron. Lett. , 1 , 21 - 23
    20. 20)
      • G. Nikandish , A. Medi .
        20. Nikandish, G., Medi, A.: ‘Analysis of integral non-linearity errors in two-step analogue-to-digital converters’, IET Circuits Devices Syst.., 2012, 6, (1), pp. 18.
        . IET Circuits Devices Syst.. , 1 , 1 - 8
    21. 21)
      • Z. Zhangming , Q. Zheng , L. Maliang .
        21. Zhangming, Z., Zheng, Q., Maliang, L., et al: ‘A 6-to-10 Bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 µm CMOS’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (3), pp. 689696.
        . IEEE Trans. Circuits Syst. I, Regul. Pap. , 3 , 689 - 696
    22. 22)
      • X. Wenyan , W. Qi , L. Li .
        22. Wenyan, X., Qi, W., Li, L., et al: ‘A 6-bit 320-MS/s 2-bit/cycle SAR ADC with tri-level charge redistribution’. IEEE Int. Conf. Anti-Counterfeiting, Security, and Identification (ASID), September 2015, pp. 7175.
        . IEEE Int. Conf. Anti-Counterfeiting, Security, and Identification (ASID) , 71 - 75
    23. 23)
      • H.-Y. Tai , C.-H. Tsai , P.-Y. Tsai .
        23. Tai, H.-Y., Tsai, C.-H., Tsai, P.-Y., et al: ‘A 6 bit 1 GS/s two-step SAR ADC in 40 nm CMOS’, IEEE Trans. Circuits Syst. II, Express Briefs, 2014, 61, (5), pp. 339343.
        . IEEE Trans. Circuits Syst. II, Express Briefs , 5 , 339 - 343
    24. 24)
      • H. Xue , W. Qi , Y. Huazhong .
        24. Xue, H., Qi, W., Huazhong, Y., et al: ‘A single channel, 6 bit 410 MS/s 3 bits/stage asynchronous SAR ADC based on resistive DAC’, J. Semicond., 2015, 36, (5), p. 055010(1–7).
        . J. Semicond. , 5 , 055010
    25. 25)
      • X. Jixuan , C. Chixiao , Y. Fan .
        25. Jixuan, X., Chixiao, C., Fan, Y., et al: ‘A 6 b 600 MS/s SAR ADC with a new switching procedure of 2 b/stage and self-locking comparators’, J. Semicond., 2015, 36, (5), p. 055009(1–7).
        . J. Semicond. , 5 , 055009
    26. 26)
      • H. Xue , W. Qi , Y. Huazhong .
        26. Xue, H., Qi, W., Huazhong, Y., et al: ‘A single channel, 6 bit 230 MS/s asynchronous SAR ADC based on 2 bits/stage’, J. Semicond., 2014, 35, (7), p. 075005(1–6).
        . J. Semicond. , 7 , 075005
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0499
Loading

Related content

content/journals/10.1049/iet-cds.2016.0499
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address