Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Method for designing ternary adder cells based on CNFETs

  • Author(s): Sepehr Tabrizchi 1, 2 ; Atiyeh Panahi 3 ; Fazel Sharifi 4 ; Keivan Navi 1, 2, 3 ; Nader Bagherzadeh 5
    • View affiliations
  • Source: Volume 11, Issue 5, September 2017, p. 465 – 470
    DOI:  10.1049/iet-cds.2016.0443 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Received 09/11/2016, Accepted 13/03/2017, Revised 26/02/2017, Published 16/03/2017

Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field-effect transistors (CNFETs) can easily be utilised for multiple-Vt circuit designs. In this study, a novel energy-efficient method for designing one-digit adder is proposed. The suggested design employ ternary multiplexers to select and of input trits for the output node values. This study describes the novel ternary multiplexer, and cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state-of-the-art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

Inspec keywords: multiplexing equipment; adders; carbon nanotube field effect transistors; logic design

Other keywords: scalable threshold voltage; digital system designer; successor cell; HSPICE simulation; one-digit adder design; carbon nanotube field-effect transistor; ternary multiplexer; energy-efficient method; ternary adder cell; C; standard CNFET technology; multiple valued logic; size 32 nm; predecessor cell; multiple-Vt circuit design; power consumption

Subjects: Semiconductor device modelling, equivalent circuits, design and testing; Fullerene, nanotube and related devices; Digital circuit design, modelling and testing; Other field effect devices; Logic circuits

References

    1. 1)
      • 17. Castro, L.C., John, D., Pulfrey, D., et al: ‘Method for predicting fT for carbon nanotube FETs’, IEEE Trans. Nanotechnol., 2005, 4, (6), pp. 699–704.
    2. 2)
      • 26. Moaiyeri, M.H., Doostaregan, A., Navi, K.: ‘Design of energy-efficient and robust ternary circuits for nanotechnology’, IET Circuits Devices Syst., 2011, 5, (4), pp. 285–296.
    3. 3)
      • 27. Gelao, G., Marani, R., Diana, R., et al: ‘A semiempirical SPICE model for n-type conventional CNTFETs’, IEEE Trans. Nanotechnol., 2011, 10, (3), pp. 506–512.
    4. 4)
      • 2. Hoeneisen, B., Mead, C.A.: ‘Fundamental limitations in microelectronics – I. MOS technology’, Solid-State Electron., 1972, 15, (7), pp. 819–829.
    5. 5)
      • 11. Hurst, S.L.: ‘Multiple-valued logic – its status and its future’, IEEE Trans. Comput., 1984, 100, (12), pp. 1160–1179.
    6. 6)
      • 20. Tabrizchi, S., AZIMI, N., Keivan, N.: ‘Design a novel ternary half adder and multiplier based on carbon nano-tube field effect transistors (CNTFETs)’, Frontiers, 2016, 1, pp. 423–433.
    7. 7)
      • 28. Marani, R., Perri, A.: ‘A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software’, Curr. Nanosci., 2011, 7, pp. 245–253.
    8. 8)
      • 30. Gelao, G., Marani, R., Pizzulli, L., et al: ‘A model to improve analysis of CNTFET logic gates in verilog-A-part II: dynamic analysis’, Curr. Nanosci., 2015, 11, (6), pp. 770–783.
    9. 9)
      • 18. Kim, Y.B., Kim, Y.-B., Lombardi, F.: ‘A novel design methodology to optimize the speed and power of the CNTFET circuits’. 2009 52nd IEEE Int. Midwest Symp. on Circuits and Systems IEEE, 2009.
    10. 10)
      • 22. Deng, J., Wong, H.-S.P.: ‘A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application – part I: model of the intrinsic channel region’, IEEE Trans. Electron Devices, 2007, 54, (12), pp. 3186–3194.
    11. 11)
      • 14. Keshavarzian, P., Sarikhani, R.: ‘A novel CNTFET-based ternary full adder’, Circuits Syst. Signal Process., 2014, 33, (3), pp. 665–679.
    12. 12)
      • 21. Deng, J., Wong, H.-S.P.: ‘A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application – part II: full device model and circuit performance benchmarking’, IEEE Trans. Electron Devices, 2007, 54, (12), pp. 3195–3205.
    13. 13)
      • 8. Kameyama, M.: ‘Toward the age of beyond-binary electronics and systems’. Multiple-Valued Logic, 1990, Proc. of the Twentieth Int. Symp. on IEEE, 1990.
    14. 14)
      • 25. Raychowdhury, A., Roy, K.: ‘Carbon nanotube electronics: design of high-performance and low-power digital circuits’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2007, 54, (11), pp. 2391–2401.
    15. 15)
      • 15. Guo, J., Koswatta, S.O., Neophytou, N., et al: ‘Carbon nanotube field-effect transistors’, Int. J. High Speed Electron. Syst., 2006, 16, pp. 897–912.
    16. 16)
      • 1. Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: ‘Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits’, Proc. IEEE, 2003, 91, (2), pp. 305–327.
    17. 17)
      • 10. Razavi, H., Bou-Ghazale, S.: ‘Design of a fast CMOS ternary adder’. Proc. IEEE Int. Symp. on Multiple-Valued Logic (ISMVL), 1987.
    18. 18)
      • 9. Sridharan, K., Gurindagunta, S., Pudi, V.: ‘Efficient multiternary digit adder design in CNTFET technology’, IEEE Trans. Nanotechnol., 2013, 12, (3), pp. 283–287.
    19. 19)
      • 23. Taheri, M., Akbar, R., Safaei, F., et al: ‘Comparative analysis of adiabatic full adder cells in CNFET technology’, Eng. Sci. Technol., 2016, 19, (4), pp. 2119–2128.
    20. 20)
      • 13. SeyyedAshkanEbrahimi, P.K., SaeidSorouri, M.: ‘Low power CNTFET-based ternary full adder cell for nanoelectronics’, Int. J. Soft Comput. Eng.(IJSCE), 2012, 2, (2), pp. 291–295.
    21. 21)
      • 4. Lent, C.S., Tougaw, P.D., Porod, W., et al: ‘Quantum cellular automata’, Nanotechnology, 1993, 4, p. 49.
    22. 22)
      • 19. Raychowdhury, A., Roy, K.: ‘Carbon-nanotube-based voltage-mode multiple-valued logic design’, IEEE Trans. Nanotechnol., 2005, 4, (2), pp. 168–179.
    23. 23)
      • 5. Likharev, K.: ‘Single-electron transistors: electrostatic analogs of the DC SQUIDS’, IEEE Trans. Magn., 1987, 23, (2), pp. 1142–1145.
    24. 24)
      • 12. McEuen, P.L., Fuhrer, M.S., Park, H.: ‘Single-walled carbon nanotube electronics’, IEEE Trans. Nanotechnol., 2002, 1, (1), pp. 78–85.
    25. 25)
      • 33. Sharifi, F., Moaiyeri, M.H., Navi, K., et al: ‘Robust and energy-efficient carbon nanotube FET-based MVL gates: a novel design approach’, Microelectron. J., 2015, 46, (12), pp. 1333–1342.
    26. 26)
      • 6. Akturk, A., Pennington, G., Goldsman, N., et al: ‘Electron transport and velocity oscillations in a carbon nanotube’, IEEE Trans. Nanotechnol., 2007, 6, (4), pp. 469–474.
    27. 27)
      • 3. Lin, S., Kim, Y.-B., Lombardi, F.: ‘A novel CNTFET-based ternary logic gate design’. 2009 IEEE 52nd IEEE Int. Midwest Symp. on Circuits and Systems, 2009.
    28. 28)
      • 32. Marani, R., Perri, A.G.: ‘A DC model of carbon nanotube field effect transistor for CAD applications’, Int. J. Electron., 2012, 99, (3), pp. 437–444.
    29. 29)
      • 16. Iijima, S.: ‘Helical microtubules of graphitic carbon’, Nature, 1991, 354, (6348), pp. 56–58.
    30. 30)
      • 29. Gelao, G., Marani, R., Pizzulli, L., et al: ‘A model to improve analysis of CNTFET logic gates in verilog-A-part I: static analysis’, Curr. Nanosci., 2015, 11, (4), pp. 515–526.
    31. 31)
      • 31. Marani, R., Gelao, G., Perri, A.G.: ‘Modelling of carbon nanotube field effect transistors oriented to SPICE software for A/D circuit design’, Microelectron. J., 2013, 44, (1), pp. 33–38.
    32. 32)
      • 7. Smith, K.C.: ‘Multiple-valued logic: a tutorial and appreciation’, IEEE Comput., 1988, 21, (4), pp. 17–27.
    33. 33)
      • 24. Tabrizchi, S., Sharifi, H., Sharifi, F., et al: ‘A novel design approach for ternary compressor cells based on CNTFETs’, Circuits Syst. Signal Process., 2015, 35, pp. 1–13.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0443
Loading

Related content

content/journals/10.1049/iet-cds.2016.0443
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address