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access icon free Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amps

This study presents the design and simulation of a fully differential two-stage op-amp in a 0.18 μm complementary metal–oxide–semiconductor process with a 1.8 V supply voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs) are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two-stage op-amp. A comprehensive analysis is provided for differential-mode gain, common-mode gain, power supply rejection ratio, input-referred noise, input offset, frequency response and the effect of using SLTs on DC-gain sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post-layout and Monte Carlo simulation results show that the proposed op-amp has better performance than the state-of-the-art designs.

References

    1. 1)
      • 30. Gray, P.R., Meyer, R.G.: ‘Analysis and design of analog integrated circuits’ (John Wiley and Sons, 2001).
    2. 2)
      • 15. Razavi, B.: ‘Design of analog CMOS integrated circuits’ (McGraw-Hill, New York, 2001).
    3. 3)
      • 10. Gulati, K., Lee, H.S.: ‘A high-swing CMOS telescopic operational amplifier’, IEEE J. Solid-State Circuits, 1998, 33, (12), pp. 20102019.
    4. 4)
      • 6. He, L., Zhu, G., Long, F., et al: ‘A multibit delta–sigma modulator with double noise-shaped segmentation’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2015, 62, (3), pp. 241245.
    5. 5)
      • 33. Grasso, A.D., Palumbo, G., Pennisi, S.: ‘Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2006, 53, (10), pp. 10441048.
    6. 6)
      • 13. Raikos, G., Vlassis, S.: ‘Low-voltage bulk-driven input stage with improved transconductance’, Int. J. Circuit Theory Appl., 2011, 39, (3), pp. 327339.
    7. 7)
      • 23. Ferreira, L.H.C., Pimenta, T.C., Moreno, R.L.: ‘An ultra-low-voltage ultra-low-power CMOS miller OTA with rail-to-rail input/output swing’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2007, 54, (10), pp. 843847.
    8. 8)
      • 5. Cho, Y.K., Park, B.H.: ‘Single op-amp second-order loop filter for continuous-time delta–sigma modulators’, Electron. Lett., 2015, 51, (8), pp. 619621.
    9. 9)
      • 28. Ning, N., Yang, F., Zhiling, S., et al: ‘A low-sensitivity negative resistance load fully differential OTA under low voltage 40 nm CMOS logic process’, Chin. Sci. Pap., 2012, 688, pp. 17.
    10. 10)
      • 29. Assaad, R.S., Silva-Martinez, J.: ‘Enhancing general performance of folded cascode amplifier by recycling current’, Electron. Lett., 2007, 43, (23), pp. 12.
    11. 11)
      • 24. Saxena, V., Baker, R.J.: ‘Indirect compensation techniques for three-stage fully-differential op-amps’. 53rd IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2010, pp. 588591.
    12. 12)
      • 3. Zuo, L., Islam, S.K.: ‘Low-voltage bulk-driven operational amplifier with improved transconductance’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2013, 60, (8), pp. 20842091.
    13. 13)
      • 4. Esparza-Alfaro, F., Pennisi, S., Palumbo, G., et al: ‘Low-power class-AB CMOS voltage feedback current operational amplifier with tunable gain and bandwidth’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2014, 61, (8), pp. 574578.
    14. 14)
      • 31. Ho, K.P., Chan, C.F., Choy, C.S., et al: ‘Reversed nested Miller compensation with voltage buffer and nulling resistor’, IEEE J. Solid-State Circuits, 2003, 38, (10), pp. 17351738.
    15. 15)
      • 21. Farahmand, S., Shamsi, H.: ‘Positive feedback technique for DC-gain enhancement of folded cascode op-amps’. IEEE 10th Int. New Circuits and Systems Conf. (NEWCAS), 2012, pp. 261264.
    16. 16)
      • 17. Khameh, H., Shamsi, H.: ‘On the design of a low-voltage twostage OTA using bulk-driven and positive feedback techniques’, Int. J. Electron., 2012, 99, (9), pp. 13091315.
    17. 17)
      • 26. Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: ‘Matching properties of MOS transistors’, IEEE J. Solid-State Circuits, 1989, 24, (5), pp. 14331439.
    18. 18)
      • 9. Asloni, M., Hadidi, K., Khoei, A.: ‘Design of a new folded cascode op-amp using positive feedback and bulk amplification’, IEICE Trans. Electron., 2007, 90, (6), pp. 12531257.
    19. 19)
      • 1. Zhao, X., Fang, H., Ling, T., et al: ‘Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain’, AEU-Int. J. Electron. Commun., 2015, 69, (3), pp. 685690.
    20. 20)
      • 16. Akbari, M., Hashemipour, O.: ‘Enhancing transconductance of ultra-low-power two-stage folded cascode OTA’, Electron. Lett., 2014, 50, (21), pp. 15141516.
    21. 21)
      • 22. Yavari, M.: ‘Hybrid cascode compensation for two-stage CMOS op-amps’, IEICE Trans. Electron., 2005, 88, (6), pp. 11611165.
    22. 22)
      • 25. Furth, P.M., Thota, N.R., Nammi, V.H., et al: ‘Low dropout (LDO) voltage regulator design using split-length compensation’. IEEE 55th Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2012, pp. 10881091.
    23. 23)
      • 19. Pude, M., Mukund, P.R., Burleson, J.: ‘Positive feedback for gain enhancement in sub-100 nm multi-GHz CMOS amplifier design’, Int. J. Circuit Theory Appl., 2013, 43, (1), pp. 111124.
    24. 24)
      • 8. Johns, D., Martin, K.: ‘Analog integrated circuit design’ (JohnWiley & Sons, 1997).
    25. 25)
      • 20. Tran, P.T., Hess, H.L., Noren, K.V., et al: ‘Gain-enhancement differential amplifier using positive feedback’. IEEE 55th Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2012, pp. 718721.
    26. 26)
      • 18. Khameh, H., Mirzaie, H., Shamsi, H.: ‘A new two-stage op-amp using hybrid cascode compensation, bulk-driven, and positive feedback techniques’. 8th IEEE Int. NEWCAS Conf. (NEWCAS), 2010, pp. 109112.
    27. 27)
      • 2. Neag, M., Oneţ, n, Kovács, I., et al: ‘Comparative analysis of simulation-based methods for deriving the phase- and gain-margins of feedback circuits with op-amps’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2015, 62, (3), pp. 625634.
    28. 28)
      • 14. Ferreira, L.H.C., Sonkusale, S.R.: ‘A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2014, 61, (6), pp. 16091617.
    29. 29)
      • 12. Kulej, T., Khateb, F.: ‘Bulk-driven adaptively biased OTA in 0.18 μm CMOS’, Electron. Lett., 2015, 51, (6), pp. 458460.
    30. 30)
      • 11. Bult, K., Geelen, G.J.G.M.: ‘A fast-settling CMOS op-amp for SC circuits with 90-dB DC gain’, IEEE J. Solid-State Circuits, 1990, 25, (6), pp. 13791384.
    31. 31)
      • 7. Sahoo, B.D., Inamdar, A.: ‘Thermal-noise-canceling switched-capacitor circuit’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2016, 63, (7), pp. 628632.
    32. 32)
      • 27. Assaad, R.S., Silva-Martinez, J.: ‘The recycling folded cascode: A general enhancement of the folded cascode amplifier’, IEEE J. Solid-State Circuits, 2009, 44, (9), pp. 25352542.
    33. 33)
      • 32. Grasso, A.D., Palumbo, G., Pennisi, S.: ‘Advances in reversed nested miller compensation’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2007, 54, (7), pp. 14591470.
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