http://iet.metastore.ingenta.com
1887

MIPSfpga: using a commercial MIPS soft-core in computer architecture education

MIPSfpga: using a commercial MIPS soft-core in computer architecture education

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

References

    1. 1)
      • 1. Imagination University Program – Resources’, https://community.imgtec.com/university/resources, accessed February 2017.
        .
    2. 2)
      • 2. Imagination Technologies Ltd.: ‘MIPS32 microAptiv™ UP Processor Core Family Datasheet’, 31 July 2013.
        .
    3. 3)
      • 3. ARM: ‘AMBA 3 AHB-Lite Protocol Specification’, 2006.
        .
    4. 4)
      • S. Harris , R. Owen , E. Sedano .
        4. Harris, S., Owen, R., Sedano, E., et al: ‘MIPSfpga: hands-on learning on a commercial soft-core’. 11th European Workshop on Microelectronics Education (EWME), Southampton, England, May 2016, pp. 15.
        . 11th European Workshop on Microelectronics Education (EWME) , 1 - 5
    5. 5)
      • 5. Digilient Inc.: ‘Nexys4 DDR™ FPGA Board Reference Manual’, 11 September 2014.
        .
    6. 6)
      • 6. Terasic Inc.: ‘DE2-115 User Manual’, 2013.
        .
    7. 7)
      • D. Harris , S. Harris . (2007)
        7. Harris, D., Harris, S.: ‘Digital design and computer architecture’ (Elsevier Science and Technology, 2007, 2nd edn. 2012).
        .
    8. 8)
      • Z. Kakakhel , S. Harris , D. Harris .
        8. Kakakhel, Z., Harris, S., Harris, D.: ‘MIPSfpga: an unobfuscated commercial MIPS core and SoC that runs Linux’’. Embedded World 2016, Nuremberg, Germany, February 2016.
        . Embedded World 2016
    9. 9)
      • 9. Altera – NIOS-II Processor’, https://www.altera.com/products/processors/overview.html, accessed February 2017.
        .
    10. 10)
      • 10. Xilinx – MicroBlaze Soft Processor Core’, http://www.xilinx.com/products/design-tools/microblaze.html, accessed February 2017.
        .
    11. 11)
      • 11. ARM – Cortex M0 Design Start’, http://www.arm.com/products/designstart/index.php, accessed February 2017.
        .
    12. 12)
      • 12. Oracle – OpenSPARC’, http://www.oracle.com/technetwork/systems/opensparc/index.html, accessed February 2017.
        .
    13. 13)
      • 13. ‘Aeroflex Gaisler – LEON series Softcores’, http://www.gaisler.com/, accessed February 2017.
        .
    14. 14)
      • A. Waterman , Y. Lee , D.A. Patterson .
        14. Waterman, A., Lee, Y., Patterson, D.A., et al: ‘The RISC-V Instruction Set Manual, Volume I: User-Level ISA’, version 2.0, 2014.
        .
    15. 15)
      • 15. ‘OpenCores – OpenRISC’, http://opencores.org/or1k/Main_Page, accessed February 2017.
        .
    16. 16)
      • P. Bulić , V. Guštin , D. Šonc .
        16. Bulić, P., Guštin, V., Šonc, D., et al: ‘An FPGA-based integrated environment for computer architecture’, Comput. Appl. Eng. Educ., 2013, 21, (1), pp. 2635.
        . Comput. Appl. Eng. Educ. , 1 , 26 - 35
    17. 17)
      • H. Oztekin , F. Temurtas , A. Gulbag .
        17. Oztekin, H., Temurtas, F., Gulbag, A.: ‘BZK.SAU: implementing a hardware and software-based computer architecture simulator for educational purpose’. Proc. 2nd Int. Conf. Computer Design and Applications, Qinhuangdao, China, June 2010, pp. 490497.
        . Proc. 2nd Int. Conf. Computer Design and Applications , 490 - 497
    18. 18)
      • K. Abe , T. Tateoka , M. Suzuki .
        18. Abe, K., Tateoka, T., Suzuki, M., et al: ‘An integrated laboratory for processor organization, compiler design and computer networking’, IEEE Trans. Educ., 2004, 47, (3), pp. 311320.
        . IEEE Trans. Educ. , 3 , 311 - 320
    19. 19)
      • S. Petit , J. Sahuquillo , M.E. Gómez .
        19. Petit, S., Sahuquillo, J., Gómez, M.E., et al: ‘A research-oriented course on advanced multicore architecture: contents and active learning methodologies’, J. Parallel Distrib. Comput., 2017.
        . J. Parallel Distrib. Comput.
    20. 20)
      • B. Nikolic , Z. Radivojevic , J. Djordjevic .
        20. Nikolic, B., Radivojevic, Z., Djordjevic, J., et al: ‘A survey and evaluation of simulators suitable for teaching courses in computer architecture and organization’, IEEE Trans. Educ., 2009, 52, (4), pp. 449458.
        . IEEE Trans. Educ. , 4 , 449 - 458
    21. 21)
      • (2004)
        21. The Joint Task Force on Computing Curricula, IEEE Computer Society/ACM: ‘Computer engineering 2004 – curriculum guidelines for undergraduate degree programs in computer engineering’ (IEEE Computer Society, 2004).
        .
    22. 22)
      • H.B.C. Kumar , P. Ravi , G. Modi .
        22. Kumar, H.B.C., Ravi, P., Modi, G., et al: ‘120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board’. Int. Symp. on Field-Programmable Gate Arrays, Monterey, USA, February 2017.
        . Int. Symp. on Field-Programmable Gate Arrays
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0383
Loading

Related content

content/journals/10.1049/iet-cds.2016.0383
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address