© The Institution of Engineering and Technology
In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.
References
-
-
1)
-
2. Imagination Technologies Ltd.: ‘MIPS32 microAptiv™ UP Processor Core Family Datasheet’, 31 July 2013.
-
2)
-
3)
-
8. Kakakhel, Z., Harris, S., Harris, D.: ‘MIPSfpga: an unobfuscated commercial MIPS core and SoC that runs Linux’’. Embedded World 2016, Nuremberg, Germany, February 2016.
-
4)
-
19. Petit, S., Sahuquillo, J., Gómez, M.E., et al: ‘A research-oriented course on advanced multicore architecture: contents and active learning methodologies’, J. Parallel Distrib. Comput., 2017.
-
5)
-
21. The Joint Task Force on Computing Curricula, IEEE Computer Society/ACM: ‘Computer engineering 2004 – curriculum guidelines for undergraduate degree programs in computer engineering’ (IEEE Computer Society, 2004).
-
6)
-
6. Terasic Inc.: ‘DE2-115 User Manual’, 2013.
-
7)
-
22. Kumar, H.B.C., Ravi, P., Modi, G., et al: ‘120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board’. Int. Symp. on Field-Programmable Gate Arrays, Monterey, USA, February 2017.
-
8)
-
10. ‘Xilinx – MicroBlaze Soft Processor Core’, .
-
9)
-
1. ‘Imagination University Program – Resources’, .
-
10)
-
16. Bulić, P., Guštin, V., Šonc, D., et al: ‘An FPGA-based integrated environment for computer architecture’, Comput. Appl. Eng. Educ., 2013, 21, (1), pp. 26–35.
-
11)
-
3. ARM: ‘AMBA 3 AHB-Lite Protocol Specification’, 2006.
-
12)
-
9. ‘Altera – NIOS-II Processor’, .
-
13)
-
14. Waterman, A., Lee, Y., Patterson, D.A., et al: ‘The RISC-V Instruction Set Manual, Volume I: User-Level ISA’, , 2014.
-
14)
-
12. ‘Oracle – OpenSPARC’, .
-
15)
-
11. ‘ARM – Cortex M0 Design Start’, .
-
16)
-
5. Digilient Inc.: ‘Nexys4 DDR™ FPGA Board Reference Manual’, 11 September 2014.
-
17)
-
18)
-
17. Oztekin, H., Temurtas, F., Gulbag, A.: ‘BZK.SAU: implementing a hardware and software-based computer architecture simulator for educational purpose’. Proc. 2nd Int. Conf. Computer Design and Applications, Qinhuangdao, China, June 2010, pp. 490–497.
-
19)
-
20. Nikolic, B., Radivojevic, Z., Djordjevic, J., et al: ‘A survey and evaluation of simulators suitable for teaching courses in computer architecture and organization’, IEEE Trans. Educ., 2009, 52, (4), pp. 449–458.
-
20)
-
18. Abe, K., Tateoka, T., Suzuki, M., et al: ‘An integrated laboratory for processor organization, compiler design and computer networking’, IEEE Trans. Educ., 2004, 47, (3), pp. 311–320.
-
21)
-
4. Harris, S., Owen, R., Sedano, E., et al: ‘MIPSfpga: hands-on learning on a commercial soft-core’. 11th European Workshop on Microelectronics Education (EWME), Southampton, England, May 2016, pp. 1–5.
-
22)
-
7. Harris, D., Harris, S.: ‘Digital design and computer architecture’ (Elsevier Science and Technology, 2007, 2nd edn. 2012).
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0383
Related content
content/journals/10.1049/iet-cds.2016.0383
pub_keyword,iet_inspecKeyword,pub_concept
6
6