access icon free Double gate symmetric tunnel FET: investigation and analysis

© The Institution of Engineering and Technology
Received 20/08/2016, Accepted 08/12/2016, Revised 27/11/2016, Published 09/12/2016

In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF-state current and subthreshold swing (SS) are significantly high for the double gate Ge source/drain symmetric p–n–p tunnel field effect transistor (TFET) with a silicon channel without n+ pockets at the source- and drain-channel interfaces. They further establish that using pockets at the source- and drain-channel interface, the Ge source/drain symmetric p–n–p TFET exhibits a 130 times improvement in I ON/I OFF ratio and a 26% reduction in SS due to the two orders of magnitude reduction in its OFF-state current when compared with the one without the n+ pockets. The results also indicate that the Ge source/drain symmetric p–n–p TFET suffers from a low output conductance at low drain voltages. Since the proposed device exhibits bidirectional current flow, it can be easily integrated with the conventional complementary metal-oxide semiconductor technology.

Inspec keywords: field effect transistors; tunnel transistors; CMOS integrated circuits; germanium

Other keywords: calibrated 2D simulations; complementary metal-oxide semiconductor technology; subthreshold swing; bidirectional current flow; TFET; double gate source-drain symmetric p-n-p tunnel field effect transistor; source-channel interfaces; off-state current; CMOS technology; Ge; drain-channel interfaces; SS

Subjects: Other field effect devices; Insulated gate field effect transistors; CMOS integrated circuits

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