access icon free Implementation of a low-power LVQ architecture on FPGA

This study presents an architecture-optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low-power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors’ architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.

Inspec keywords: neural chips; reconfigurable architectures; field programmable gate arrays; circuit optimisation; low-power electronics; neural net architecture; embedded systems

Other keywords: embedded architecture; low-power LVQ architecture; power consumption; architecture-optimising methodology; low-power-energy architecture; ergonomic utilisation; LVQ topology; Xpower tool; LVQ neural network; energy consumption; decision circuitry; analytical power model; FPGA software design tools

Subjects: Computer architecture; Digital circuit design, modelling and testing; Logic circuits; Logic and switching circuits; Neural net devices; Neural nets (circuit implementations)

References

    1. 1)
      • 9. Dumonteix, Y., Bajot, Y., Mehrez, H.: ‘A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic’. Materials Research Society Symp. – Proc., 2001, vol. 626, pp. 878881.
    2. 2)
      • 12. Chalbi, N., Ben Khalifa, K., Boubaker, M., et al: ‘Implementation of a novel LVQ neural network architecture on FPGA’, Int. J. Artif. Intell. Soft Comput., 2010, 2, (3), pp. 163173..
    3. 3)
      • 17. Xilinx: ‘Vivado design suite tutorial, high-level synthesis’, (UG871 (v2012.2) 20 August 2012), pp. 1113.
    4. 4)
      • 14. Betul, B., Guo, Z., Najjar, W.: ‘Impact of loop unrolling on area, throughput and clock frequency in ROCCC: C to VHDL compiler for FPGAs’, Reconfigurable Computing :Architectures and Applications, 2006, pp. 401412.
    5. 5)
      • 21. Koeing, A., Guenther, A., Doege, J., et al: ‘Cell library of scalable neural network classifiers for rapid low power vision and cognition systems design’. Int. Conf. Knowledge Based Intelligent Electronic Systems, Proc., Kes, Brighton, UK, 2000, pp. 275282.
    6. 6)
      • 25. Kohonen, T.: ‘Self-organization maps’ (Springer, New York, 2001, 3rd edn.), vol. 30.
    7. 7)
      • 22. Kugler, M., Lopes, M.: ‘A configware approach for the implementation of a LVQ neural network’, Int. J. Comput. Intell. Res., 2007, 3, (1), pp. 2125.
    8. 8)
      • 13. Boubaker, M., BenKhalifa, K., Girau, B., et al: ‘On-line arithmetic based reprogrammable hardware implementation of LVQ neural network for alertness classification’, IJCSNS Int. J. Comput. Sci. Netw. Secur., 2008, 8, (3), pp. 260266.
    9. 9)
      • 5. Modi, S.S., Wilson, P.R., Brown, A.D.: ‘Power scalable implementation of artificial neural networks’. 12th IEEE Int. Conf. Electronics, Circuits and Systems, Gammarth, 11–14 December 2005, pp. 14.
    10. 10)
      • 15. Thibault, S., Pellerin, D.: ‘Optimizing impulse C code for performance’. Technical Report, Impulse Accelerated Technologies, Inc., 2004, pp. 110.
    11. 11)
      • 3. Janardan, M., Indranil, S.: ‘Artificial neural networks in hardware: a survey of two decades of progress’, Neurocomputing, 2010, 74, pp. 239255.
    12. 12)
      • 7. Mazzoni, L.: ‘Power aware design for embedded systems’, IEE Electron. Syst. Softw., 2003, 1, pp. 1217.
    13. 13)
      • 2. Weeks, M., Freeman, M., Moulds, A., et al: ‘Developing hardware based applications using presence’, in ‘Perspectives in pervasive computing’ (IET Press, London, 2005), pp. 469474.
    14. 14)
      • 6. Jinde, S., Thorat, D., Samrat, S.: ‘Neural network implementation using FPGAs’, Int. J. Comput. Sci. Inf. Technol., 2014, 5, (3), pp. 34313433.
    15. 15)
      • 23. Najoua, C., Mohamed, B., Hedi, B.M.: ‘Analytical dynamic power model for LUT based components’. Int. Conf. Design & Technology of Integrated Systems in Nanoscale Era, Gammarth, 2012, pp. 16, 10.1109/DTIS.2012.6232957.
    16. 16)
      • 1. Girau, B., Torres-Huitzil, C.: ‘Massively distributed digital implementation of an integrate and fire legion network for visual scene segmentation’, Neurocomputing, 2007, 70, (7–9), pp. 11861197.
    17. 17)
      • 24. Najoua, C., Mohamed, B., Hedi, B.M.: ‘Power estimation model based on grouping components in field programmable gate array circuit’, IET Circuits Devices Syst., 2012, 6, (6), pp. 437446, 10.1049/iet-cds.2011.0367.
    18. 18)
      • 20. Vipin, T., Shrikant, V., Nilay, K.: ‘Hardware efficient implementation of neural network’, Int. Refereed J. Eng. Sci. (IRJES), 2013, 2, (5), pp. 2023.
    19. 19)
      • 11. Moukhlis, S., Elrharras, A., Hamdoun, A.: ‘FPGA implementation of artificial neural networks’, Int. J. Comput. Sci. Issues (IJCSI), 2014, 11, (2), pp. 237240.
    20. 20)
      • 16. Guohui, W.: ‘Catapult C synthesis work flow tutorial’ (ELEC 522 Advanced VLSI Design, Rice University, Version 1.3, 2010), pp. 120.
    21. 21)
      • 26. An, F., Akazawa, T., Yamasaki, S., et al: ‘VLSI realization of learning vector quantization with hardware/software codesign for different applications’, Jpn. J. Appl. Phys., 2015, 54, (4), pp. 15.
    22. 22)
      • 19. Rafael, G., Joaquín, C., Franciso, B., et al: ‘Artificial neural network implementation on a single FPGA of a pipelined on-line back-propagation’. Proc. 13th Int. Symp. System Synthesis, 2000, pp. 225230.
    23. 23)
      • 27. Lachmair, J., Merenyi, E., Porrmann, M., et al: ‘A reconfigurable neuroprocessor for self-organizing feature maps’, Neurocomputing, 2013, 112, pp. 189199.
    24. 24)
      • 18. Kurra, S., Singh, N.K., Ranjan, P.P.: ‘The impact of loop unrolling on controller delay in high level synthesis’. In Proc. of the Conf. Design, Automation and Test in Europe, 2007, pp. 16.
    25. 25)
      • 31. Kisi, O.: ‘Multi-layer perceptrons with Levenberg–Marquardt training algorithm for suspended sediment concentration prediction and estimation’, J. Hydrol. Sci., 2004, 49, (6), pp. 10251040.
    26. 26)
      • 30. Xilinx: ‘Xilinx power tools tutorial’, (UG733 (v1.0), 15 March 2010), pp. 128.
    27. 27)
      • 10. Boubaker, M., Akil, M., Ben Khalifa, K., et al: ‘Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices’, Neural Comput. and Appl., 2010, 19, (2), pp. 283297.
    28. 28)
      • 29. NanoBoard NB2 series datasheet, March 2015.
    29. 29)
      • 28. NanoBoard 3000 series datasheet, 5 March 2014.
    30. 30)
      • 4. Evangelos, S., Francesco, G., Cameron, P., et al: ‘Power analysis of large-scale, real-time neural networks on SpiNNaker’. The 2013 Int. Joint Conf. Neural Networks (IJCNN), Dallas, TX, 4–9 August 2013, pp. 18.
    31. 31)
      • 8. Pandya, A.S., Agarwal, A., Kim, P.K.: ‘Low power design of the neuroprocessor’. Lecture Notes in Artificial Intelligence, Springer Verlag, Heidelberg, Germany, 2003(subseries of LNCS, 2774), Part 2, pp. 856862.
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