access icon free Event-driven detection method based on pseudo-differential self-timed inverter-based incremental sigma-delta analogue-to-digital converter

In this study, an event-driven detection method based on pseudo-differential self-timed inverter-based incremental sigma-delta analogue-to-digital converter (IDC) is proposed and analysed, which is adapted for sparse signal measurement. A judgment module is implemented to detect whether the input signal of the measurement system is beyond a threshold or not. The input signal will be converted by the IDC only when it is beyond the threshold. A pseudo-differential self-timed inverter-based IDC is also proposed in the event-driven detection technique. The proposed event-driven detection technique is designed and simulated with 1.5-V supply voltage. The IDC achieves 12.8-bit ENOB at 2-KS/s conversion rate and consumes 45 μW. Its figure-of-merit is 3.1 pJ/step and input range is 0–2.4 V. The sparse signal measurement system with the proposed event-driven detection method based on self-timed IDC is implemented. The average power consumption of the system is related to the event ratio. With the event ratios of 10, 20 and 30%, its power consumption will be 30, 34 and 37 μW, respectively. The event-driven detection method improves the power efficiency of the sparse signal measurement system.

Inspec keywords: invertors; measurement systems; sigma-delta modulation

Other keywords: word length 12.8 bit; event-driven detection method; power 37 muW; power 30 muW; pseudodifferential self-timed inverter; voltage 0 V to 2.4 V; input signal detection; ENOB; sparse signal measurement system; power 45 muW; power 34 muW; incremental sigma-delta analogue-to-digital converter; self-timed IDC; voltage 1.5 V

Subjects: A/D and D/A convertors; Signal processing and conditioning equipment and techniques; A/D and D/A convertors; Power electronics, supply and supervisory circuits

References

    1. 1)
      • 8. Li, H., Boling, C.S., Mason, A.J.: ‘CMOS amperometric ADC with high sensitivity, dynamic range and power efficiency for air quality monitoring’, IEEE Trans. Biomed. Circuits Syst., 2016, 10, (4), pp. 817827.
    2. 2)
      • 1. Fazela, F., Fazelb, M., Stojanovic, M.: ‘Compressed sensing in random access networks with applications to underwater monitoring’, PHYCOM, 2012, 5, (2), pp. 148160.
    3. 3)
      • 17. Chae, Y., Han, G.: ‘Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator’, IEEE J. Solid-State Circuits, 2009, 44, (2), pp. 458472.
    4. 4)
      • 12. Sepke, T., Holloway, P., Sodini, C.G., et al: ‘Noise analysis for comparator-based circuits’, IEEE Trans. Circuits Syst. I Regul. Pap., 2009, 56, (3), pp. 541553.
    5. 5)
      • 15. Huang, M.C., Liu, S.I.: ‘A fully-differential comparator-based switched-capacitor delta-sigma modulator’, IEEE Trans. Circuits Syst. II Express Briefs, 2009, 56, (5), pp. 369373.
    6. 6)
      • 24. Huang, M., Liu, S.: ‘A 10-MS/s-to-100-kS/s power-scalable fully differential CBSC 10-bit pipelined ADC with adaptive biasing’, IEEE Trans. Circuits Syst. II Express Briefs, 2010, 57, (1), pp. 1115.
    7. 7)
      • 14. Shin, S.K., You, Y.S., Lee, S.H., et al: ‘A fully-differential zero-crossing-based 1.2 V 10b 26 MS/s pipelined ADC in 65 nm CMOS’. IEEE Symp. VLSI Circuits, Hawaii, the USA, June 2008, pp. 218219.
    8. 8)
      • 16. Tawfiq, M., Sunwoo, K., Lakdawala, H., et al: ‘A 630 W zero-crossing-based delta-sigma ADC using switched-resistor current sources in 45 nm CMOS’. Proc. IEEE CICC, San Jose, the USA, September 2009, pp. 14.
    9. 9)
      • 21. Sebastian, Z., Christian, M., Robert, W., et al: ‘A 0.039 mm inverter-based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-ΔΣ-ADC in 65 nm CMOS using power- and area-efficient design techniques’, IEEE J. Solid-State Circuits, 2014, 49, (7), pp. 15481560.
    10. 10)
      • 20. Thomas, C.: ‘A 15-bit 140-W scalable-bandwidth inverter-based ΔΣ modulator for a MEMS microphone with digital output’, IEEE J. Solid-State Circuits, 2013, 48, (7), pp. 16051614.
    11. 11)
      • 3. Yip, M., Chandrakasan, A.P.: ‘A resolution-reconfigurable 5-to-10-bit 0.4-to-1 v power scalable sar adc for sensor applications’, IEEE J. Solid-State Circuits, 2013, 48, (6), pp. 14531464.
    12. 12)
      • 6. Ali, A., Katelijn, V., Bruce, A.W., et al: ‘A high-resolution low-power incremental adc with extended range for biosensor arrays’, IEEE J. Solid-State Circuits, 2010, 45, (6), pp. 10991110.
    13. 13)
      • 13. Brooks, L., Lee, H.S.: ‘A zero-crossing-based 8b 200 MS/s pipelined ADC. Solid-state circuits’. IEEE ISSCC Digest of Technical Papers, San Francisco, the USA, February 2007, pp. 460615.
    14. 14)
      • 11. Fiorenza, J.K., Sepke, T., Holloway, P., et al: ‘Comparator-based switched-capacitor circuits for scaled cmos technologies’, IEEE J. Solid-State Circuits, 2006, 41, (12), pp. 26582668.
    15. 15)
      • 9. Genov, R., Stanacevic, M., Naware, M., et al: ‘16-channel integrated potentiostat for distributed neurochemical sensing’, IEEE Trans. Circuits Syst. I Regul. Pap., 2006, 53, (11), pp. 23712376.
    16. 16)
      • 18. Luo, H., Han, Y., Cheung, R.C.C.: ‘A 0.8-V 230-μW 98-dB DR inverter-based ΣΔ modulator for audio applications’, IEEE J. Solid-State Circuits, 2013, 48, (10), pp. 24302441.
    17. 17)
      • 10. Quiquempoix, V., Deval, P., Barreto, A., et al: ‘A low-power 22-bit incremental adc’, IEEE J. Solid-State Circuits, 2006, 41, (7), pp. 15621571.
    18. 18)
      • 19. Michel, F., Steyaert, M.S.J.: ‘A 250 mV 7.5 μW 61 dB SNDR sc ΔΣ modulator using near-threshold-voltage-biased inverter amplifiers in 130 nm cmos’, IEEE J. Solid-State Circuits, 2012, 47, (3), pp. 709721.
    19. 19)
      • 22. Chen, C., Tan, Z., Pertijs, M.A.P.: ‘A 1 V 14b self-timed zero-crossing-based incremental ΔΣ ADC’. IEEE Int. Solid-State Circuits Conf., San Francisco, the USA, February 2013, pp. 274275.
    20. 20)
      • 23. Wulff, C., Trond, Y.: ‘CBSC pipelined ADC with comparator preset, and comparator delay compensation’. I Proc. IEEE NORCHIP Conf., Trondheim, Norway, November 2009, pp. 14.
    21. 21)
      • 7. Gore, A., Chakrabartty, S., Pal, S., et al: ‘A multichannel femtoampere-sensitivity potentiostat array for biosensing applications’, IEEE Trans. Circuits Syst. I Regul. Pap., 2006, 53, (11), pp. 23572363.
    22. 22)
      • 2. Baliga, J., Ayre, R.W.A., Hinton, K., et al: ‘Green cloud computing: balancing energy in processing, storage, and transport’, Proc. IEEE, 2011, 99, (1), pp. 149167.
    23. 23)
      • 5. Yousry, R., Chen, M.S., Chang, M.C.F., et al: ‘An architecture-reconfigurable 3b-to-7b 4 GS/s-to-1.5 GS/s ADC using subtractor interleaving’. Proc. of IEEE ASSCC, Resorts World Convention Centre, Singapore, November 2013, pp. 285288.
    24. 24)
      • 4. Zhu, Z., Qiu, Z., Liu, M., et al: ‘A 6-to-10-bit 0.5 v-to-0.9 v reconfigurable 2 ms/s power scalable sar adc in 0.18 cmos’, IEEE Trans. Circuits Syst. I Regul. Pap., 2015, 62, (3), pp. 689696.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0270
Loading

Related content

content/journals/10.1049/iet-cds.2016.0270
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading