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access icon free Design of multiplierless prototype filter for two-channel filter bank using hybrid method in FCSD space

  • Author(s): Ila Sharma 1 ; Anil Kumar 1, 2 ; Girish Kumar Singh 3 ; Heung-No Lee 2
    • View affiliations
    • Affiliations: 1: PDPM Indian Institute of Information Technology Design and Manufacturing Jabalpur, Jabalpur 482011, MP, India ;
      2: School of Electrical Engineering and Computer Science (EECS), Gwangju Institute of Science and Technology (GIST) Korea, Gwangju 61005, Korea ;
      3: Indian Institute of Technology Roorkee, Roorkee 247667, Uttrakhand, India
  • Source: Volume 11, Issue 1, January 2017, p. 29 – 40
    DOI:  10.1049/iet-cds.2016.0124 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Received 01/04/2016, Accepted 05/10/2016, Revised 15/09/2016, Published 01/01/2017

In this work, a hybrid method-based design of multiplierless two-channel filter bank has been proposed with a given stopband attenuation (A s) and roll-off factor. Windowing method has been used for efficient design of a prototype filter with novelty of exploiting quantised coefficients in canonical sign digit (CSD) and factorised canonical sign digit (FCSD) space by merging the concept of particle swarm optimisation and artificial bee colony algorithm. The quantised filter coefficients are optimised by varying cut-off frequency such that the magnitude response of prototype filter is approximately reduced to 0.707 at quadrature frequency. The implemented filter is synthesised using target field programmable gate arrays XC3S500E-4-FG320 on Xilinx Spartan 3E starter board. The performances of designed prototype filter is compared with the earlier published works in terms of reconstruction error, amplitude distortion, slices, flip-flops, four-input lookup tables and adders. The synthesis results demonstrate that the significant reduction in hardware is achieved in term of adder gain. For filter order, N = 32, and word length 12, the adder gain achieved in CSD and FCSD is 41.77 and 43.07%, respectively, while for N = 30, it is 35.44% in CSD and 36.70% in FCSD, respectively.

Inspec keywords: particle swarm optimisation; channel bank filters; ant colony optimisation; circuit optimisation

Other keywords: particle swarm optimisation; canonical sign digit space; factorised canonical sign digit space; quantised filter coefficients; hybrid method-based design; windowing method; FCSD space; artificial bee colony algorithm; multiplierless prototype filter design; multiplierless two-channel filter bank; target field programmable gate arrays XC3S500E-4-FG320; Xilinx Spartan 3E starter board; roll-off factor; stopband attenuation

Subjects: Filters and other networks; Optimisation techniques

References

    1. 1)
    2. 2)
      • 34. George, J.T., Elias, E.: ‘Design of multiplier-less continuously variable bandwidth sharp FIR filters using modified harmony search algorithm’, Int. J. Inf. Technol. Manag., 2014, 14, (1), pp. 5–25.
    3. 3)
    4. 4)
      • 18. Tan, F., Zhang, T., Gao, C., et al: ‘Optimal design of cosine modulated filter banks using quantum-behaved particle swarm optimization algorithm’. 2011 Fourth International Congress on Image and Signal Processing IEEE, 2011, pp. 2280–2284.
    5. 5)
    6. 6)
      • 9. Shaeen, K., Elias, E.: ‘Prototype filter design approaches for near perfect reconstruction cosine modulated filter banks – a review’, J. Signal Process. Syst., 2014, 81, (2), pp. 183–195.
    7. 7)
    8. 8)
      • 19. Zhang, T., Tan, F., Yi, C., et al: ‘An optimized design of non-uniform filter banks based on memetic algorithm’. 2013 Sixth International Congress on Image and Signal Processing (CISP) IEEE, 2013, pp. 1194–1199.
    9. 9)
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • 24. Hewlitt, R.M., Swartzlantler, E.S.: ‘Canonical signed digit representation for FIR digital filters’. 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528) IEEE, 2000, pp. 416–426.
    14. 14)
    15. 15)
    16. 16)
    17. 17)
    18. 18)
    19. 19)
    20. 20)
      • 37. Karaboga, D.: ‘An idea based on honey bee swarm for numerical optimization’, Tech. Rep., TR06, Erciyes Univ., 2005, (TR06), p. 10.
    21. 21)
    22. 22)
    23. 23)
    24. 24)
      • 35. Misra, D., Dhabal, S., Venkateswaran, P.: ‘Quadrature mirror filter bank with canonical signed digit representation using linear optimization algorithm’. Proc. of the 2015 Third Int. Conf. on Computer, Communication, Control and Information Technology (C3IT) IEEE, 2015, pp. 1–6.
    25. 25)
    26. 26)
    27. 27)
    28. 28)
    29. 29)
    30. 30)
      • 27. Goel, N., Nandi, A.: ‘Design of FIR filter using FCSD representation’. 2015 IEEE Int. Conf. on Computational Intelligence & Communication Technology IEEE, 2015, pp. 617–620.
    31. 31)
    32. 32)
    33. 33)
      • 46. Sharma, I., Kumar, A., Singh, G.K.: ‘An efficient method for designing multiplier-less non-uniform filter bank based on hybrid method using CSE technique’, Circuits Syst. Signal Process., 2016, pp. 1–23, doi: 10.1007/s00034-016-0351-2.
    34. 34)
      • 40. Jheng, K.-Y., Jou, S.-J., Wu, A.-Y.: ‘A design flow for multiplier less linear-phase FIR filters: from system specification to Verilog code’. 2004 IEEE Int. Symp. on Circuits and Systems (IEEE Cat. No.04CH37512) IEEE, 2004, pp. V-293–V-296.
    35. 35)
      • 5. Jain, A., Saxena, R., Saxena, S.C.: ‘A simple alias-free QMF system with near-perfect reconstruction’, J. INDIAN Inst. Sci., 2005, 85, (1), pp. 1–10.
    36. 36)
    37. 37)
    38. 38)
      • 41. Yli-Kaakinen, J., Saramaki, T.: ‘A systematic algorithm for the design of multiplier less FIR filters’. ISCAS 2001. The 2001 IEEE Int. Symp. on Circuits and Systems (Cat. No.01CH37196) IEEE, 2001, pp. 185–188.
    39. 39)
    40. 40)
    41. 41)
    42. 42)
      • 3. Mitra, S.K., Kuo, Y.: ‘Digital signal processing: a computer-Based approach’ (McGraw-Hill, New York, 2006, 2nd edn.).
    43. 43)
      • 33. Bindiya, T.S., Elias, E.: ‘Design of multiplier-less sharp transition width non-uniform filter banks using gravitational search algorithm’, Int. J. Electron., 2014, 102, (1), pp. 48–70.
    44. 44)
    45. 45)
    46. 46)
    47. 47)
    48. 48)
      • 6. Kumar, A., Singh, G.K., Anand, R.S.: ‘Near perfect reconstruction quadrature mirror filter’, Int. J. Electr. Comput. Energ. Electron. Commun. Eng., 2008, 2, (1), pp. 25–28.
    49. 49)
    50. 50)
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