access icon free Carbon nanotube FET-based low-delay and low-power multi-digit adder designs

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.

Inspec keywords: ternary logic; carbon nanotube field effect transistors; low-power electronics; logic design; adders

Other keywords: single-trit adder design; field-effect transistor-based device technology; low-complexity multidigit adders; carbon nanotube FET; multivalued logic; low-delay low-power multidigit adder design; multiternary digit CNTFET-based adder design; ternary half-adder; CNTFET technology; CNTFET-based full-adder; unary operators; metal oxide semiconductor FET; arithmetic circuit design; CNTFET-based HA; CNTFET-based carry lookahead adder; MOSFET; extensive HSPICE simulations; conditional sum-carry lookahead; multitrit design; power-delay product; CNTFET-based conditional sum adder

Subjects: Logic and switching circuits; Other field effect devices; Logic circuits; Digital circuit design, modelling and testing; Fullerene, nanotube and related devices; Logic design methods

References

    1. 1)
      • 15. Parhami, B.: ‘Computer arithmetic: algorithms and hardware designs’ (Oxford University Press, 2010).
    2. 2)
      • 37. Karmakar, S., Gogna, M., Suarez, E., et al: ‘Three-state quantum dot gate field-effect transistor in silicon-on-insulator’, IET Circuits Devices Syst., 2015, 9, (2), pp. 111118.
    3. 3)
      • 19. Karmakar, S., Chandy, J.A., Jain, F.C.: ‘Design of ternary logic combinational circuits based on quantum dot gate FETs’, IEEE Trans. VLSI Syst., 2013, 21, (5), pp. 793806.
    4. 4)
      • 25. Pudi, V., Sridharan, K.: ‘Low complexity design of ripple carry and Brent-Kung adders in QCA’, IEEE Trans. Nanotechnol., 2012, 11, (1), pp. 105119.
    5. 5)
      • 35. Chan, H.L.E., Bhattacharya, M., Mazumder, P.: ‘Mask-programmable multiple-valued logic gate using resonant tunnelling diodes’, IEE Proc. Circuits Devices Syst., 1996, 143, (5), pp. 289294.
    6. 6)
      • 10. Moaiyeri, M.H., Mirzaee, R.F., Navi, K., et al: ‘Efficient CNTFET-based ternary full adder cells for nanoelectronics’, Nano-Micro Lett., 2011, 3, (1), pp. 4350.
    7. 7)
      • 14. Miller, D.M., Thornton, M.A.: ‘Multiple valued logic: concepts and representations’ (Morgan & Claypool Publishers, 2008).
    8. 8)
      • 23. Cho, H., Swartzlander, E.E.: ‘Adder designs and analyses for quantum-dot cellular automata’, IEEE Trans. Nanotechnol., 2007, 6, (3), pp. 374383.
    9. 9)
      • 2. Novoselov, K.S., Geim, A.K., Morozov, S.V., et al: ‘Electric field effect in atomically thin carbon films’, Science, 2004, 306, (5696), pp. 666669.
    10. 10)
      • 34. Kim, T.H., Persaud, R., Kim, C.H.: ‘Silicon odometer: an on-chip reliability monitor for measuring frequency degradation of digital circuits’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 874880.
    11. 11)
      • 17. Dhande, A.P., Ingole, V.T.: ‘Design and Implementation of 2-bit Ternary ALU slice’. Proc. Int. Conf. IEEE-Science Electronics, Technology Information and Telecommunication, 2005, pp. 1721.
    12. 12)
      • 9. Navi, K., Rashtian, M., Khatir, A., et al: ‘High speed capacitor-inverter based carbon nanotube full adder’, Nanoscale Res. Lett., 2010, 5, pp. 859862.
    13. 13)
      • 12. Sridharan, K., Gurindagunta, S., Pudi, V.: ‘Efficient multiternary digit adder design in CNTFET technology’, IEEE Trans. Nanotechnol., 2013, 12, (3), pp. 283287.
    14. 14)
      • 36. Klein, M., Mol, J.A., Verdujin, J., et al: ‘Ternary logic implemented on a single dopant atom field effect silicon transistor’, Appl. Phys. Lett., 2010, 96, p. 043107.
    15. 15)
      • 5. Kundu, S., Mohanty, S.P., Ranganathan, N.: ‘Design methodologies for nanoelectronic digital and analogue circuits – guest editorial’, IET Circuits Devices Syst., 2013, 7, (5), pp. 221222.
    16. 16)
      • 24. Cho, H., Swartzlander, E.E.: ‘Adder and multiplier designs in quantum-dot cellular automata’, IEEE Trans. Comput., 2009, 58, (6), pp. 721727.
    17. 17)
      • 11. Keshavarzian, P., Sarikhani, R.: ‘A novel CNTFET-based ternary full adder’, Circuits Syst. Signal Process., 2014, 33, pp. 665679.
    18. 18)
      • 8. Lin, S., Kim, Y.-B., Lombardi, F.: ‘CNTFET-based design of ternary logic gates and Arithmetic circuits’, IEEE Trans. Nanotechnol., 2011, 10, (2), pp. 217225.
    19. 19)
      • 22. Labrado, C., Thapliyal, H.: ‘Design of adder and subtractor circuits in majority logic-based field-coupled quantum nanocomputing’, IET Electron. Lett., 2016, 52, pp. 464466.
    20. 20)
      • 1. Iijima, S.: ‘Helical microtubules of graphitic carbon’, Nature, 1991, 354, (6348), pp. 5658.
    21. 21)
      • 28. Stanford University CNTFET model, Website: Stanford University, Stanford, CA, 2008). Available at http://nano.stanford.edu/model_stan_cnt.htm.
    22. 22)
      • 29. Lin, Y., Appenzeller, J., Knoch, J., et al: ‘High-performance carbon nanotube field effect transistor with tunable polarities’, IEEE Trans. Nanotechnol., 2005, 4, (5), pp. 418489.
    23. 23)
      • 32. Raychowdhury, A., Vivek De, K., Borkar, S.Y., et al: ‘Variation tolerance in a multichannel carbon-nanotube transistor for high-speed digital circuits’, IEEE Trans. Electron Devices, 2009, 56, (3), pp. 383392.
    24. 24)
      • 3. Tans, S.J., Verschueren, A.R.M., Dekker, C.: ‘Room-temperature transistor based on a single carbon nanotube’, Nature, 1998, 393, pp. 4952.
    25. 25)
      • 18. Murotiya, S., Gupta, A.: ‘Design of high speed ternary full adder and three-input xor circuits using cntfets’. Proc. of 28th Int. Conf. on VLSI Design, 2015, pp. 292297.
    26. 26)
      • 20. Cotofana, S., Lageweg, C., Vassiliadis, S.: ‘Addition-related arithmetic operations via controlled transport of charge’, IEEE Trans. Comput., 2005, 54, (3), pp. 243256.
    27. 27)
      • 31. Krupke, R., Heinrich, F., Lohneysen, H.V., et al: ‘Separation of metallic from semiconducting single-walled carbon nanotubes’, Science, 2003, 301, (5631), pp. 344347.
    28. 28)
      • 30. Ben-Jamaa, M.H., Mohanram, K., De Micheli, G.: ‘An efficient gate library for ambipolar CNTFET logic’, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 2011, 30, (2), pp. 242255.
    29. 29)
      • 7. Moaiyeri, M.H., Doostaregan, A., Navi, K.: ‘Design of energy-efficient and robust ternary circuits for nanotechnology’, IET Circuits Devices Syst., 2011, 5, (4), pp. 285296.
    30. 30)
      • 27. Raychowdhury, A., Roy, K.: ‘Carbon nanotube electronics: design of high-performance and low-power digital circuits’, IEEE Trans. Circuits Syst. I Reg. Pap., 2007, 54, (11), pp. 23912401.
    31. 31)
      • 4. Bachtold, A., Hadley, P., Nakanishi, T., et al: ‘Logic circuits with carbon-nanotube transistors’, Science, 2001, 294, (5545), pp. 13171320.
    32. 32)
      • 21. Tougaw, P.D., Lent, C.S.: ‘Logical devices implemented using quantum cellular automata’, J. Appl. Phys., 1994, 75, (3), pp. 18181825.
    33. 33)
      • 16. Deng, J., Philip Wong, H.-S.: ‘A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application – Part I: model of the intrinsic channel region’, IEEE Trans. Electron Devices, 2007, 54, (12), pp. 31863194.
    34. 34)
      • 13. Jasemi, M., Mirzaee, R.F., Navi, K., et al: ‘Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic’, IET Circuits Devices Syst., 2015, 9, (5), pp. 343352.
    35. 35)
      • 26. Cocorullo, G., Corsonello, P., Frustaci, F., et al: ‘Design of efficient BCD adders in quantum dot cellular automata’, IEEE Trans. Circuits Syst. II Express Briefsdoi: 10.1109/TCSII.2016.2580901, early access.
    36. 36)
      • 6. Raychowdhury, A., Roy, K.: ‘Carbon-Nanotube-based voltage-mode multiple-valued logic design’, IEEE Trans. Nanotechnol., 2005, 4, (2), pp. 168179.
    37. 37)
      • 33. Xing, C.J., Yin, W.Y., Liu, L., et al: ‘Investigation on self-heating effect in carbon nanotube field-effect transistors’, IEEE Trans. Electron Devices, 2011, 58, (2), pp. 523529.
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