This study presents new prototyped evaluation results for the authors’ proposed power analysis attack countermeasure architecture based on decoupling individual sensitive modules with low current consumption. The proposed architecture includes a switch box module to randomise internal connections, mixing residual information that may leak through non-ideal switch elements and uneven charge cycles. The two implementations evaluated are a printed circuit board (PCB) developed using stand-alone CMOS components and the post-layout simulation of a circuit developed in 0.18 µm TSMC CMOS technology using Cadence. Both systems were able to protect a decoupled 8-bit XOR module from a correlation power analysis performed using traces collected at the power supply rail for at least 8000 plaintext inputs. The results show that the countermeasure is suitable for both on-chip and on-board designs. Analysis of the measurements collected from the PCB test system demonstrates the need to balance the charge/discharge frequency of the decoupling elements against the operational frequency of the decoupled modules. From the layout, an individual decoupling element was found to be similar in size to the decoupled 8-bit XOR module, with all four decoupling elements occupying a total of 51% of the layout area. This percentage is expected to decrease in the context of larger, more complex systems.

References

1. 1)
  - 10. Kaps, J.-P.: ‘Chai-tea, cryptographic hardware implementation of xTEA’. Proc. INDOCRYPT 2008, 2008, vol. 5365, pp. 363–375.
2. 2)
  - 32. Seo-Kyu, K.: ‘Smart cards having protection circuits therein that inhibit power analysis attacks and methods of operating same’. U.S. Patent 7620823, 2009.
3. 3)
  - 35. Muresan, R., Gregori, S.: ‘Protection circuit against differential power analysis attacks for smart cards’, IEEE Trans. Comput., 2008, 57, (11), pp. 1540–1549 (doi: 10.1109/TC.2008.107).
4. 4)
  - 2. Kim, J., Lee, B.J., Yoo, S.K.: ‘Design of a real-time encryption module for secure data protection of wearable healthcare devices’. Proc. 2013 35th Annual Int. Conf. of the IEEE EMBC, 2013, pp. 2283–2286.
5. 5)
  - 9. Abdelhalim, M.B., El-Mahallawy, M., Ayyad, M., et al: ‘Implementation of a modified lightweight cryptographic TEA algorithm in RFID system’. Proc. ICITST 2011, 2011, pp. 509–513.
6. 6)
  - 18. Avital, M., Dagan, H., Keren, O., et al: ‘Randomized multitopology logic against differential power analysis’, IEEE Trans. VLSI Syst., 2015, 23, (4), pp. 702–711 (doi: 10.1109/TVLSI.2014.2320154).
7. 7)
  - 19. Bonnecaze, A., Liardet, P., Venellli, A.: ‘AES side-channel countermeasure using random tower field constructions’, Des. Codes Cryptog. (Netherlands), 2013, 69, (3), pp. 331–349 (doi: 10.1007/s10623-012-9670-x).
8. 8)
  - 6. Alioto, M., Polie, M., Rocchi, S.: ‘Power analysis attacks to cryptographic circuits: a comparative analysis of DPA and CPA’. Proc. of ICM'08, 2008, pp. 333–336.
9. 9)
  - 15. Kim, H., Rozic, V., Verbauwhede, I.: ‘Three phase dynamic current mode logic: a more secure DyCML to achieve a more balanced power consumption’. Proc. WISA, 2012(LNCS, 7690), pp. 68–81.
10. 10)
  - 34. Baker, R.J.: ‘CMOS circuit design, layout, and simulation’ (John Wiley & Sons. Inc., 2010, 3rd edn.).
11. 11)
  - 28. Corsonello, P., Perri, S., Margala, M.: ‘An integrated countermeasure against differential power analysis for secure smart-cards’. Proc. IEEE Int. Symp. Circuits and Systems 2006, 2006, pp. 5611–5614.
12. 12)
  - 24. Shamir, A.: ‘Protecting smart cards from power analysis with detachable power supplies’. U.S. Patent 6507913, 2003.
13. 13)
  - 3. Zhou, J., Cao, Z., Dong, X., et al: ‘Security and privacy in cloud-assisted wireless wearable communications: challenges, solutions and, future directions’, IEEE Wirel. Commun. (USA), 2015, 22, (2), pp. 136–144 (doi: 10.1109/MWC.2015.7096296).
14. 14)
  - 11. Zhang, Y., Juels, A., Reiter, M.K., et al: ‘Cross-VM side channels and their use to extract private keys’. Proc. ACM Conf. on Computer and Communications Security, 2012, pp. 305–316.
15. 15)
  - 31. Weste, N.H.E., Harris, D.: ‘CMOS VLSI design: a circuits and systems perspective’ (Addison Wesley, 2011, 4th edn.2011).
16. 16)
  - 21. Lu, Y., O'Neill, M., McCanny, J.: ‘Evaluation of random delay insertion against DPA on FPGAs’, ACM Trans. Reconfigurable Technol. Syst., 2010, 4, (1), pp. 11:1–11:20 (doi: 10.1145/1857927.1857938).
17. 17)
  - 33. Johns, D.A., Martin, K.: ‘Analog integrated circuit design’ (John Wiley & Sons, Inc., 1997).
18. 18)
  - 13. Brier, E., Claiver, C., Oliver, F.: ‘Correlation power analysis with a leakage model’. CHES 2004, 2004 (LNCS, 3156), pp. 16–29.
19. 19)
  - 26. Mayhew, M., Muresan, R.: ‘Integrated capacitor switchbox for security protection’. Proc. IEEE Int. Symp. Circuits and Systems 2012, 2012, pp. 1452–1455.
20. 20)
  - 25. Tokunaga, C., Blaauw, D.: ‘Security encryption systems with a switched capacitor current equalizer’, IEEE JSSC, 2010, 45, pp. 23–31.
21. 21)
  - 12. Lee, J.-W., Chung, S.-C., Chang, H.-C., et al: ‘Efficient power analysis resistant dual-field elliptic curve cryptographic processor using heterogeneous dual-processing element architecture’, IEEE Trans. VLSI Syst., 2014, 22, (1), pp. 49–61 (doi: 10.1109/TVLSI.2013.2237930).
22. 22)
  - 27. Mayhew, M., Muresan, R.: ‘On-chip nanoscale capacitor decoupling architectures for hardware security’, IEEE TETC, 2014, 2, pp. 4–15.
23. 23)
  - 29. Muresan, R., Mayhew, M.: ‘On-chip decoupling architecture with variable nMOS gate capacitance for security protection’. 2013 IEEE 56th MWSCAS, 2013, pp. 1342–1345.
24. 24)
  - 23. Hubert, G.T.M.: ‘Current source for cryptographic processor’. U.S. Patent 7571492, 2009.
25. 25)
  - 28. Monteiro, C., Takahashi, Y., Sekine, T.: ‘Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level’, Microelectron. J., 2013, 44, (6), pp. 496–503 (doi: 10.1016/j.mejo.2013.04.003).
26. 26)
  - 14. Verbauwhede, I.M., Tiri, K.J.V.: ‘Dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis’. U.S. Patent 7418468, 2009.
27. 27)
  - 22. Baddam, K., Zwolinski, M.: ‘Evaluation of dynamic voltage and frequency scaling as a differential power analysis countermeasure’. Proc. IEEE Int. Conf. on VLSI Design 2007, 2007, pp. 854–859.
28. 28)
  - 8. Gandolfi, K., Mourter, C., Oliver, F.: ‘Electromagnetic analysis: concrete results’. Proc. CHES 2001, 2001(LNCS, 2162), pp. 251–261.
29. 29)
  - 1. Kocher, P., Lee, R., McGraw, G., et al: ‘Security as a new dimension in embedded system design’. Proc. of Design Automation Conf. 2004, 2004, pp. 753–760.
30. 30)
  - 7. Kocher, P.: ‘Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems’. Proc. Advances in Cryptology – CRYPTO'96, 1996, pp. 104–113.
31. 31)
  - 5. Kocher, P., Jaffe, J., Jun, B.: ‘Differential power analysis’. Advances in Cryptology – CRYPTO'99, 1999(LNCS, 1666), pp. 388–397.
32. 32)
  - 16. Razafindraibe, A., Robert, M., Maurine, P.: ‘Improvement of dual rail logic as a countermeasure against DPA’. Proc. 2007 IFIP Int. Conf. on VLSI, 2007, pp. 270–275.
33. 33)
  - 20. Maghrebi, H., Guilley, S., Prouff, E., et al: ‘Register leakage masking using gray code’. Proc. HOST 2012, 2012, pp. 37–42.
34. 34)
  - 4. Rankl, W.: ‘Smart card applications’ (Wiley, 2007).
35. 35)
  - 30. NIST: ‘Federal Information Processing Standards Publication 197, Announcing the Advanced Encryption Standard (AES)’, 2001.

Implementation of a decoupling based power analysis attack countermeasure

References

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