access icon free Low-power consumption ternary full adder based on CNTFET

This paper presents low-power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the CNTs, the threshold voltage simple control is the best property to implement ternary logic circuits. Low-complexity, low-power consumption and low-power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carry-generation unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, the final proposed TFA has reduced the power consumption significantly and results in 86.92 and 97% reductions in terms of the PDP in comparison with two recent proposed designs.

Inspec keywords: circuit complexity; adders; carbon nanotube field effect transistors; field effect transistor circuits; voltage control; low-power electronics

Other keywords: sum-generation unit; noise margins; threshold voltage simple control; THSGs; carbon nanotube field-effect transistors; ternary logic circuits; ternary half sum generators; carry-generation unit; CNTFET technology; low-power delay product; low-power consumption ternary full adder; HSPICE; low-power consumption; low circuit complexity; size 32 nm; TFA; PDP

Subjects: Logic circuits; Voltage control; Logic and switching circuits

References

    1. 1)
    2. 2)
      • 15. Dhande, A.P., Ingole, V.T.: ‘Design and implementation of 2-bit ternary ALU slice’. Proc. Int. Conf. IEEE-Sciences Electronic, Technologies of Information and Telecommunications, Tunisia, March 2005, pp. 1721.
    3. 3)
      • 20. Kordrostami, Z., Sheikhi, M.H.: ‘Fundamental physical aspects of carbon nanotube transistors’, in Marulanda, J.M. (ED.): ‘Carbon nanotubes’ (INTECH Open Access Publisher, University Campus STeP Ri, Rijeka, Croatia, 2010), pp. 169186.
    4. 4)
    5. 5)
    6. 6)
      • 18. Ebrahimi, S.A., Keshavarzian, P., Sorouri, S., et al: ‘Low power CNTFET-based ternary full adder cell for nanoelectronics’, Int. J. Soft Comput., 2012, 2, (2), pp. 291295.
    7. 7)
    8. 8)
    9. 9)
    10. 10)
      • 7. Inokawa, H., Fujiwara, A., Takahashi, Y.: ‘A multiple-valued logic with merged single-electron and MOS transistors’ (IEDM Technical Digest, Washington DC USA, Des. 2001), pp. 7.2.17.2.4.
    11. 11)
      • 4. Kamar, Z., Nepal, K.: ‘Noise margin-optimized ternary CMOS SRAM delay and sizing characteristics’. Proc. IEEE Int. Midwest Symp. Circuits and Systems, Seattle WA, August 2010, pp. 801804.
    12. 12)
    13. 13)
    14. 14)
    15. 15)
      • 9. Deng, J.: ‘Device modeling and circuit performance evaluation for nanoscale devices’, PhD thesis, Stanford University, 2007.
    16. 16)
    17. 17)
    18. 18)
    19. 19)
    20. 20)
    21. 21)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2015.0264
Loading

Related content

content/journals/10.1049/iet-cds.2015.0264
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading