The study presents the algorithm design, non-ideal effect analysis, architectural analysis and design, circuit analysis and design of an iterative frequency calibration system that corrects frequencies consuming very low energy. The method is based on measuring the ‘fraction’ portion when an oscillator frequency (typically of a radio frequency oscillator) is divided by a fixed reference frequency. It then compares the obtained fraction value with the target fraction value (target frequency divided by the same reference) and finally corrects the oscillator frequency so as to converge it to the target. A salient feature of the proposed architecture of the system is the absence of elements in the radio frequency path which is considered to be the main source of power consumption. The system can be used in applications that do not require stringent phase-locking e.g. wireless sensor nodes. Test of the calibration system has been performed in conjunction with a Medical Implant Communication Service (MICS) band (402–405 MHz) oscillator. Successful convergence has been achieved over a wide range of sampler delay variation and oscillator jitter, which are the circuit level non-idealities that arise in the system.

References

1. 1)
  - 6. Yan, R., Sun, H., Qian, Y.: ‘Energy-aware sensor node design with its application in wireless sensor networks’, IEEE Trans. Instrum. Meas., 2013, 62, (5), pp. 1183–1191.
2. 2)
  - 20. Ghosh, A., Das, I., Halder, A.: ‘An energy efficient oscillator frequency calibration methodology based on fraction phase computation’. Proc. Int. Conf. on VLSI Design, VLSID, January 2012, pp. 85–91.
3. 3)
  - 12. Dragao, S., Leenaerts, D., Nauta, B., et al: ‘A 200 μW duty-cycled PLL for wireless sensor nodes in 65 nm CMOS’, IEEE J. Solid-State Circuits, 2010, 45, (7), pp. 1305–1315.
4. 4)
  - 26. Kossel, M.: ‘CML delay cell with extended tuning range’, IET Electron. Lett., 2007, 43, (10), pp. 568–569.
5. 5)
  - 25. Moghavemmi, M., Attaran, A.: ‘Recent advances in delay cell VCOs’, IEEE Microw. Mag., 2011, 12, (5), pp. 110–118.
6. 6)
  - 22. Logic analyzer. Available at http://en.wikipedia.org/wiki/Logic_analyzer, Accessed April 2014.
7. 7)
  - 14. Bohorquez, J.L., Chandrakasan, A.P., Dawson, J.L.: ‘A 350 μW CMOS MSK transmitter and 400 μW OOK super-regenerative receiver for medical implant communications’, IEEE J. Solid-State Circuits, 2009, 44, (4), pp. 1248–1259.
8. 8)
  - 29. Baker, R., Li, H., Boyce, D.: ‘CMOS circuit design, layout and simulation’ (IEEE Press Series on Microelectronic Syst., New York, 1998, 2nd edn.), pp. 384–387.
9. 9)
  - 21. Laser trimming. Available at http://en.wikipedia.org/wiki/Laser_trimming, Accessed April 2014.
10. 10)
  - 2. Franceschinis, M., Spirito, M.A., Tomasi, R., et al: ‘Using WSN technology for industrial monitoring: a real case’. Proc. 2nd Int. Conf. on Sensor Technologies and Applications, SENSORCOMM'08, August 2008, pp. 282–287.
11. 11)
  - 13. Dudek, P., Szczepanski, S., Hatfield, J.V.: ‘A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line’, IEEE. J. Solid State Circuits, 2000, 35, (2), pp. 240–247.
12. 12)
  - 30. Logic Analyzers. Available at http://cp.literature.agilent.com/litweb/pdf/5989-5063EN.pdf, Accessed April 2014.
13. 13)
  - 17. Ayers, J., Mayaram, K., Fiez, T.S.: ‘An ultra-low power receiver for wireless sensor networks’, IEEE J. Solid-State Circuits, 2010, 45, (9), pp. 1759–1769.
14. 14)
  - 18. Lin, T.H., Lai, Y.J.: ‘An agile VCO frequency calibration technique for a 10-GHz CMOS PLL’, IEEE J. Solid-State Circuits, 2007, 42, (2), pp. 340–349.
15. 15)
  - 16. Huang, X., Harpe, P., Wang, X., et al: ‘A 0 dBm 10 Mbps 2.4 GHz ultra-low power ASK/OOK transmitter with digital pulse shaping’. Proc. IEEE Radio Frequency Integrated Circuit Symp., RFIC 2010, May 2010, pp. 263–266.
16. 16)
  - 27. Jeong, D.Y., Chai, S.H., Song, W.C., et al: ‘CMOS current-controlled oscillators using multiple-feedback-loop ring architectures’. IEEE Int. Solid-State Circuit Conf. Digest of Technical Papers, ISSCC 1997, February 1997, pp. 386–387.
17. 17)
  - 7. Razavi, B.: ‘RF microelectronics’ (Prentice-Hall Communications Engineering and Emerging Technologies Series, Upper Saddle River, New Jersey, 1997, 1st edn.), pp. 225–227; 284–285.
18. 18)
  - 3. Bradley, P.D.: ‘An ultra-low power, high performance medical implant communication system (MICS) transceiver for implantable devices’. Proc. Biomedical Circuits and Systems Conf., BioCAS 2006, November/December 2006, pp. 158–161.
19. 19)
  - 24. Carnes, J., Vytyaz, I., Hanumolu, P.K., et al: ‘Design and analysis of noise tolerant ring oscillators using Maneatis delay cells’. Proc. IEEE Int. Conf. Electronics, Circuits Systems, ICECS 2007, December 2007, pp. 494–497.
20. 20)
  - 10. Gardner, F.M.: ‘Phaselock techniques’ (Wiley & Sons Inc., New York, 2005, 3rd edn.), pp. 312–326.
21. 21)
  - 32. Rabaey, J., Chandrakasan, A., Nikolic, B.: ‘Digital integrated circuits: a design perspective’ (Prentice-Hall of India Pvt. Ltd., New Delhi, 2006, 2nd edn.), pp. 346–348.
22. 22)
  - 15. Tanevski, M., Merli, F., Boegli, A., et al: ‘RoSe: a subgigahertz wireless sensor platform with housing integrated overmolded antenna’, IEEE Trans. Instrum. Meas., 2012, 61, (11), pp. 2982–2992.
23. 23)
  - 11. Staszewski, R.B., Muhammad, K., Leipold, D., et al: ‘All digital tx-frequency synthesizer and discrete time receiver for Bluetooth radio in 130 nm CMOS’, IEEE J. Solid-State Circuits, 2004, 39, (12), pp. 2278–2291.
24. 24)
  - 23. Pletcher, N.M., Rabaey, J.M.: ‘A 100 μW, 1.9 GHz oscillator with fully digital frequency tuning’. Proc. 31st European Solid State Circuits Conf., ESSCIRC 2005, September 2005, pp. 387–390.
25. 25)
  - 31. Razavi, B.: ‘Design of analog CMOS integrated circuits’ (Tata McGraw-Hill, New Delhi, India, 2002, 4th edn.), 11th Reprint, 2006, pp. 377–379.
26. 26)
  - 8. Khalil, W., Shashidharan, S., Copani, T., et al: ‘A 700-μA 405 MHz all-digital fractional-N frequency locked loop for ISM band applications’, IEEE Trans. Microwave Theory Tech., 2011, 59, (5), pp. 1319–1326.
27. 27)
  - 28. Turker, D.Z., Khatri, S.P., Sinencio, E.S.: ‘A DCVSL delay cell for fast low power frequency synthesis applications’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2011, 58, (6), pp. 1225–1238.
28. 28)
  - 5. Kadrolkar, A., Gao, R.X., Yan, R., et al: ‘Variable word-length coding for energy-aware signal transmission’, IEEE Trans. Instrum. Meas., 2012, 61, (4), pp. 850–864.
29. 29)
  - 1. Yuan, Y., Kam, M.: ‘Distributed decision fusion with a random-access channel for sensor network applications’, IEEE Trans. Instrum. Meas., 2004, 53, (4), pp. 1339–1344.
30. 30)
  - 19. Lee, M., Heidari, M.E., Abidi, A.A.: ‘A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution’, IEEE J. Solid-State Circuits, 2009, 44, (10), pp. 2808–2816.
31. 31)
  - 9. Yang, J., Skafidas, E.: ‘A low power MICS band phase-locked loop for high resolution retinal prosthesis’, IEEE Trans. Biomed. Circuits Syst., 2013, 7, (4), pp. 513–525.
32. 32)
  - 4. Pianegiani, F., Mingqing, H., Boni, A., et al: ‘Energy-efficient signal classification in ad-hoc wireless sensor networks’, IEEE Trans. Instrum. Meas., 2008, 57, (1), pp. 190–196.

Fraction phase based low energy frequency calibration: analysis and design

References

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