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access icon free Phase-error cancellation technique for fast-lock phase-locked loop

This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast lock in analogue phase-locked loops (PLLs). The PLL works in fast-lock mode during phase and frequency tracking, and is switched to normal mode after it is almost locked. Unstable system topology is introduced in this system for fast locking. This PEC technique is proposed to cancel the phase error when the output frequency approaches the target value. Due to the inherent oscillation nature of the intentionally designed unstable system in fast-lock mode, the time for PEC can be predicted based on some known parameters. A PLL is simulated in 0.13 µm CMOS process with 1.2 V supply to verify the proposed PEC technique. Simulation results prove that this technique can reduce at least 87% settling time as compared with conventional PLLs.

References

    1. 1)
    2. 2)
      • 12. Kuang, X.F., Wu, N.J.: ‘A fast-settling PLL frequency synthesizer with direct frequency presetting’. IEEE ISSCC Digest of Technical Papers, San Francisco, USA, February 2006, pp. 741750.
    3. 3)
      • 24. Wagdy, M.F., Sur, R.: ‘A novel SAR fast-locking digital PLL: SPICE modeling and simulations’. Proc. of the Ninth Int. Conf. on Information Technology: New Generations (ITNG 2012), Las Vegas, Nevada, April 2012, pp. 472477.
    4. 4)
      • 23. Wagdy, M.F., Nannaka, A.: ‘A novel SAR fast-locking digital PLL: behavioral modeling and simulations using VHDL-AMS’. Proc. of the 22nd Int. Conf. on Microelectronics (ICM 2010), Cairo, Egypt, December 2010, pp. 399402.
    5. 5)
    6. 6)
    7. 7)
      • 22. Sai, A., Kobayashi, Y., Saigusa, S., et al: ‘A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated Jitter in 65 nm CMOS’. IEEE ISSCC Digest of Technical Papers, San Francisco, USA, February 2012, pp. 248250.
    8. 8)
    9. 9)
    10. 10)
      • 25. Wagdy, M.F., Jayaram, S.M.: ‘A novel flash fast-locking digital PLL: verilog-AMS modeling and simulations’. Proc. of the 10th Int. Conf. on Information Technology: New Generations (ITNG 2013), Las Vegas, Nevada, April 2013, pp. 217222.
    11. 11)
    12. 12)
    13. 13)
    14. 14)
    15. 15)
    16. 16)
    17. 17)
    18. 18)
      • 9. Hsieh, F.-J., Kao, S.-K.: ‘Fast locking PLL with all-digital locked-aid circuit’. IEEE EDSSC, Hong Kong, China, December 2010, pp. 14.
    19. 19)
    20. 20)
    21. 21)
      • 2. Liu, X., Zhang, L., Zhang, L., et al: ‘A 3.45–4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications’. Proc. of IEEE MWSCAS, Texas, USA, August 2014, pp. 749752.
    22. 22)
      • 3. Ozeren, E., Zihir, S., Tasdemir, F., et al: ‘A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications’. European Microwave Integrated Circuits Conf. (EuMIC), Paris, France, September 2014, pp. 369372.
    23. 23)
      • 18. Yogesh, M., Dietl, M., Sareen, P., et al: ‘A low power, self-biased, bandwidth tracking semi-digital PLL design’. IEEE Int. Conf. on Electronics Design, Systems and Applications (ICEDSA), Kuala Lumpur, November 2012, pp. 135140.
    24. 24)
    25. 25)
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