This paper presents a low-power complementary metal–oxide–semiconductor (CMOS) clock and data recovery (CDR) integrated circuit (IC) with dynamic voltage scaling (DVS) technique. When DVS is adopted, the power efficiency can be improved by selecting the low supply voltage as possible for a given bit rate. However, the supply voltage generated from a switching regulator such as a buck converter has the ripple voltage at the switching frequency so that the CDR performance may be degraded accordingly. Thus, in this study, the analysis on the relationship among the ripple voltage, the switching frequency and the jitter tolerance (JTOL) is carried out and the appropriate ripple voltage and switching frequency of the buck converter are chosen based on the analysis. Moreover, low supply voltage circuit techniques are carefully utilised for the design of the low-power CDR IC. The CDR IC, implemented in a 0.11 μm CMOS process, shows the power efficiency of 0.97 mW/Gb/s at 4 Gb/s including the buck converter. When 4 Gb/s 2³¹−1 pseudorandom binary sequence is used, the measured bit error rate is better than 10⁻¹², the measured JTOL is 0.3 UI_pp and the measured jitter of the recovered clock is 6.1 ps_rms.