Compact noise modelling for common double-gate metal–oxide–semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry

Neha Sharan; Santanu Mahapatra

Compact noise modelling for common double-gate metal–oxide–semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry

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Author(s): Neha Sharan ¹ and Santanu Mahapatra ¹
- Affiliations: 1: Nano Scale Device Research Laboratory, Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore 560012, India
Source: Volume 10, Issue 1, January 2016, p. 62 – 67
DOI: 10.1049/iet-cds.2015.0128 , Print ISSN 1751-858X, Online ISSN 1751-8598

Received 04/02/2015, Accepted 12/07/2015, Published 01/01/2016

On the basis of the quasi-linear relationship between the surface potentials of a common double-gate metal–oxide–semiconductor field-effect transistor, a compact noise model, which is adapted to gate-oxide-thickness asymmetry, is proposed. The proposed model includes a physics-based thermal and flicker noise model. The effect of the lateral and vertical electric fields on the mobility degradation has also been taken into account for accurate noise prediction in short-channel devices. The thermal noise model is compared with the technology computer aided design (TCAD) simulation data and good agreement is observed. The proposed noise model appears to be efficient for analogue circuit simulation.

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Compact noise modelling for common double-gate metal–oxide–semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry

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