access icon free Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

© The Institution of Engineering and Technology
Received 16/12/2014, Accepted 07/12/2015, Revised 12/11/2015, Published 01/07/2016

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 µm) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm2. A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 × 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 × 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 × 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.

Inspec keywords: motion estimation; VLSI; video coding; search problems; field programmable gate arrays; application specific integrated circuits; image matching

Other keywords: Virtex-4 FPGA; block-matching motion estimation; size 0.18 mum; power 4.54 mW; Synopsys design vision tool; application specific integrated circuit; very large scale integration architecture; video encoder; field programmable gate array; Xilinx 14.2; ASIC; adaptive rood pattern search algorithm; frequency 100 MHz; peak signal-to-noise ratio; ARPS algorithm

Subjects: Image recognition; Video signal processing; Logic and switching circuits; Logic circuits; Image and video coding; Semiconductor integrated circuits

References

    1. 1)
    2. 2)
      • 17. Tourapis, A.M.: ‘Enhanced predictive zonal search for single and multiple frame motion estimation’, Electron. Imaging Int. Soc. Opt. Photonics, 2002, pp. 1069–1079.
    3. 3)
    4. 4)
      • 9. Chao, W.-M., Hsu, C.-W., Chang, Y., et al: ‘A novel hybrid motion estimator supporting diamond search and fast full search’. IEEE Int. Symp. on Circuits and Systems, 2002. ISCAS 2002, 2002, vol. 2, pp. II–492.
    5. 5)
      • 1. Koenen, R.: ‘Overview of the MPEG-4 standard’, ISO/IEC JTC1/SC29/WG11 N, 2002, 1730, pp. 11–13.
    6. 6)
      • 20. Xilinx, I.: ‘Virtex-4 fpga user guide: http://www.xilinx.com’.
    7. 7)
      • 3. Richardson, I.E.: ‘The H. 264 advanced video compression standard’ (John Wiley & Sons, 2011).
    8. 8)
      • 15. Chen, C., Shan, J., Yang, E.: ‘An improved adaptive rood pattern search algorithm based on temporal and spatial correlation’. 2012 Int. Conf. on Audio, Language and Image Processing (ICALIP), 2012, pp. 1088–1092.
    9. 9)
    10. 10)
      • 18. Li, T., Li, S., Shen, C.: ‘A novel configurable motion estimation architecture for high-efficiency mpeg-4/h.264 encoding’. Proc. 2005 Asia and South Pacific Design Automation Conf., ASP-DAC ‘05, New York, NY, USA, 2005, pp. 1264–1267.
    11. 11)
    12. 12)
    13. 13)
    14. 14)
    15. 15)
      • 23. Miyakoshi, J., Kuroda, Y., Miyama, M., et al: ‘A sub-mw MPEG-4 motion estimation processor core for mobile video application’. Custom Integrated Circuits Conf., 2003. Proc. of the IEEE 2003, 2003, pp. 181–184.
    16. 16)
    17. 17)
      • 14. Ma, K.-K., Qiu, G.: ‘An improved adaptive rood pattern search for fast block-matching motion estimation in jvt/h. 26 l’. Proc. 2003 Int. Symp. on Circuits and Systems, 2003. ISCAS'03, 2003, vol. 2, pp. II–708.
    18. 18)
      • 16. Tourapis, A.M., Au, O.C., Liou, M.L.: ‘Predictive motion vector field adaptive search technique (PMVFAST): enhancing block-based motion estimation’. Photonics West 2001-Electronic Imaging, Int. Society for Optics and Photonics, 2000, pp. 883–892.
    19. 19)
      • 24. Lin, S.: ‘Low-power motion estimation processors for mobile video application’. PhD thesis, MS thesis, Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan, 2004.
    20. 20)
      • 21. Guide, D.V.U., Version, U.: ‘March 2003, synopsys’: http://www.synopsys.com’, 2003.
    21. 21)
      • 2. Draft, I.: ‘Recommendation and final draft international standard of joint video specification (ITU-T Rec. H. 264— ISO/IEC 14496-10 avc)’, Joint Video Team (JVT) ISO/IEC MPEG ITU-T VCEG, JVTG050, 2003, 33.
    22. 22)
    23. 23)
      • 5. Babu, D., Subramanian, P., Karthikeyan, C.: ‘Performance analysis of block matching algorithms for highly scalable video compression’. Int. Symp. on Ad Hoc and Ubiquitous Computing, 2006. ISAUHC'06, 2006, pp. 179–182.
    24. 24)
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