Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform-based ultrasonic three-dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system-on-chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for real-time ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using Open Computing Language (OpenCL) targeted on Nvidia GT 750M graphical processing unit. OpenCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.

References

1. 1)
  - 35. Weber, J., Oruklu, E., Saniie, J.: ‘FPGA-based configurable frequency-diverse ultrasonic target-detection system’, IEEE Trans. Ind. Electron., 2011, 58, (3), pp. 871–879 (doi: 10.1109/TIE.2009.2030214).
2. 2)
  - 37. ‘IEEE Standards Interpretations for IEEE Std 1003.1c™-1995 IEEE Standard for Information Technology–Portable Operating System Interface (POSIX®) – System Application Program Interface (API) Amendment 2: Threads Extension (C Language)’. Available at http://standards.ieee.org/findstds/interps/1003-1c-95_int/, accessed January 2015.
3. 3)
  - 25. Saniie, J.: ‘Ultrasonic signal processing: system identification and parameter estimation of reverberant and inhomogeneous targets’. PhD thesis, Department of Electrical Engineering, Purdue University, West Lafayette, IN, 1981.
4. 4)
  - 11. González, D., Botella, G., Meyer-Baese, U., et al: ‘A low cost matching motion estimation sensor based on the NIOS II microprocessor’, Sensors, 2012, 12, (10), pp. 13126–13149 (doi: 10.3390/s121013126).
5. 5)
  - 18. Lin, Z., Chow, P.: ‘ZCluster: a Zynq-based Hadoop cluster’. IEEE Int. Conf. on Field-Programmable Technology (FPT), December 2013, pp. 450–453.
6. 6)
  - 6. Saniie, J., Oruklu, E.: ‘Introduction to special issue on novel embedded systems for ultrasonic imaging and signal processing’, IEEE Trans. Ultrason. Ferroelectr. Freq. Control, 2012, 59, (7), pp. 1329–1332(invited paper) (doi: 10.1109/TUFFC.2012.2333).
7. 7)
  - 15. Madanayake, A., Cintra, R.J., Dimitrov, V., et al: ‘Low-power VLSI architectures for DCT/DWT: precision vs approximation for HD video, biomedical, and smart antenna applications’, IEEE Circuits Syst. Mag., 2015, 15, (1), pp. 25–47 (doi: 10.1109/MCAS.2014.2385553).
8. 8)
  - 22. Amaro, J., Falcao, G., Yiu, B.Y.S., Yu, A.C.H.: ‘Portable parallel kernels for high-speed beamforming in synthetic aperture ultrasound imaging’. IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), May 2013, pp. 2688–2692.
9. 9)
  - 28. Zhao, L., Jia, Y., Xie, Y.: ‘Robust transcale decentralised estimation fusion for multisensor systems based on wavelet packet decomposition’, IET Control Theory Appl., 2014, 8, (8), pp. 585–597 (doi: 10.1049/iet-cta.2013.0285).
10. 10)
  - 7. Licciardo, G.D., Albanese, L.F.: ‘Design of a context-adaptive variable length encoder for real-time video compression on reconfigurable platforms’, IET Image Process., 2012, 6, (4), pp. 301–308 (doi: 10.1049/iet-ipr.2010.0510).
11. 11)
  - 26. Oruklu, E., Saniie, J.: ‘Dynamically reconfigurable architecture design for ultrasonic imaging’, IEEE Trans. Instrum. Meas., 2009, 58, (8), pp. 2856–2866 (doi: 10.1109/TIM.2009.2016370).
12. 12)
  - 32. Proakis, J.G., Manolakis, D.G.: ‘Digital signal processing: principles, algorithms and applications’ (Pearson, 2011, 4th edn.).
13. 13)
  - 5. Ahmad, A., Amira, A.: ‘Efficient reconfigurable architectures for 3D medical image compression’ IEEE Int. Conf. on Field-Programmable Technology, December 2009, pp. 472–474.
14. 14)
  - 16. Govindan, P., Saniie, J.: ‘Processing algorithms for three-dimensional data compression of ultrasonic radio frequency signals’, IET Signal Process., 2015, 9, (3), pp. 267–276 (doi: 10.1049/iet-spr.2014.0186).
15. 15)
  - 24. Fermin, A., Guillermo, B., Garcia, C., Prieto, M., Francisco, T.: ‘GPU-based acceleration of bio-inspired motion estimation model’, Concurrency Comput. Pract. Exp., 2013, 25, (8), pp. 1037–1056 (doi: 10.1002/cpe.2946).
16. 16)
  - 8. Meyer-Baese, U., Botella, G., Mookherjee, S., Castillo, E., García, A.: ‘Energy optimization of application-specific instruction-set processors by using hardware accelerators in semicustom ICs technology’, Microprocess. Microsyst., 2012, 36, (2), pp. 127–137 (doi: 10.1016/j.micpro.2011.06.003).
17. 17)
  - 34. Yeary, M.B., Zhang, W., Trelewicz, J.Q., Zhai, Y., McGuire, B.: ‘Theory and implementation of a computationally efficient decimation filter for power-aware embedded systems’, IEEE Trans. Instrum. Meas., 2006, 55, (5), pp. 1839–1849 (doi: 10.1109/TIM.2006.880255).
18. 18)
  - 38. ‘The Open Standard for Parallel Programming of Heterogeneous Systems’. Available at https://www.khronos.org/opencl/, accessed January 2015.
19. 19)
  - 31. Govindan, P., Saniie, J.: ‘Hardware-software co-design of 3D data compression for real-time ultrasonic imaging applications’. IEEE Int. Ultrasonics Symp. (IUS), September 2014, pp. 564–567.
20. 20)
  - 36. Hunag, L., Stotzer, E., Yi, H., Chapman, B., Chandrasekaran, S.: ‘Parallelizing ultrasound image processing using OpenMP on multicore embedded systems’. IEEE Global High Tech Congress on Electronics, November 2012, pp. 131–138.
21. 21)
  - 33. Parhi, K.K.: ‘VLSI digital signal processing systems: design and implementation’ (Wiley, 1999, 2nd edn.).
22. 22)
  - 19. Russell, M., Fischaber, S.: ‘OpenCV based road sign recognition on Zynq’. IEEE Int. Conf. on Industrial Informatics (INDIN), July 2013, pp. 596–601.
23. 23)
  - 9. Xu, M., Yao, H., Huan, X.: ‘Performance test of dual-core processor system based on NIOS II’. IEEE Symp. on Electrical & Electronics Engineering (EEESYM), June 2012, pp. 82–85.
24. 24)
  - 21. Garcia, C., Botella, G., Ayuso, F., Prieto, M., Tirado, F.: ‘Multi-GPU based on multicriteria optimization for motion estimation system’, EURASIP J. Adv. Signal Process., 2013, 1, pp. 1–12.
25. 25)
  - 30. Govindan, P., Saniie, J.: ‘Performance evaluation of 3D compression for ultrasonic nondestructive testing applications’. IEEE Int. Ultrasonics Symp. (IUS), July 2013, pp. 437–440.
26. 26)
  - 14. Darji, A., Arun, R., Merchant, S.N., Chandorkar, A.: ‘Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform’, IET Comput. Digit. Tech., 2015, 9, (2), pp. 113–123 (doi: 10.1049/iet-cdt.2013.0167).
27. 27)
  - 4. Sampson, R., Yang, M., Wei, S., Chakrabarti, C., Wenisch, T.F.: ‘Sonic Millip3De: an architecture for handheld 3D ultrasound’, IEEE Micro, 2014, 34, (3), pp. 100–108 (doi: 10.1109/MM.2014.49).
28. 28)
  - 29. Djawad, Y.A., Kiely, J., Nibouche, M., Wraith, P., Luxton, R.: ‘Robust feature extraction from impedimetric signals using wavelet packet decomposition with application to cytotoxicity testing’, IET Sci. Meas. Technol., 2012, 6, (6), pp. 456–463 (doi: 10.1049/iet-smt.2012.0009).
29. 29)
  - 13. Enfedaque, P., Auli-Llinas, F., Moure, J.C.: ‘Implementation of the DWT in a GPU through a register-based strategy’, IEEE Trans. Parallel Distrib. Syst., 2014, (99), pp. 1045–9219.
30. 30)
  - 23. Wang, G., Xiong, Y., Yun, J., Cavallaro, J.R.: ‘Accelerating computer vision algorithms using OpenCL framework on the mobile GPU – a case study’. IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), May 2013, pp. 2629–2633.
31. 31)
  - 10. González, D., Botella, G., García, C., Prieto, M., Tirado, F.: ‘Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor’, EURASIP J. Adv. Signal Process., 2013, 1, pp. 1–20.
32. 32)
  - 20. Song, C., Li, Y., Guo, J., Lei, J.: ‘Block-based two-dimensional wavelet transform running on graphics processing unit’, IET Comput. Digit. Tech., 2014, 8, (5), pp. 229–236 (doi: 10.1049/iet-cdt.2013.0141).
33. 33)
  - 2. Kim, G.D., Yoon, C., Kye, S.B., et al: ‘A single FPGA-based portable ultrasound imaging system for point-of-care applications’, IEEE Trans. Ultrason. Ferroelectr. Freq. Control, 2012, 59, (7), pp. 1386–1394 (doi: 10.1109/TUFFC.2012.2339).
34. 34)
  - 39. Jaaskelainen, P.O., De La Lama, C.S., Huerta, P., Takala, J.H.: ‘OpenCL-based design methodology for application-specific processors’. IEEE Int. Conf. on Embedded Computer Systems (SAMOS), July 2010, pp. 223–230.
35. 35)
  - 1. Kim, I., Kim, H., Griggio, F., et al: ‘CMOS ultrasound transceiver chip for high-resolution ultrasonic imaging systems’, IEEE Trans. Biomed. Circuits Syst., 2009, 3, (5), pp. 293–303 (doi: 10.1109/TBCAS.2009.2023912).
36. 36)
  - 3. Jensen, J.A., Holm, O., Jerisen, L.J., et al: ‘Ultrasound research scanner for real-time synthetic aperture data acquisition’, IEEE Trans. Ultrason. Ferroelectr. Freq. Control, 2005, 52, (5), pp. 881–891 (doi: 10.1109/TUFFC.2005.1503974).
37. 37)
  - 12. Lili, L., Wanxia, Y., Liqiang, W.: ‘The design of dinuclear sewage processor based on the Nios II’. Fifth Int. Conf. on Intelligent Networks and Intelligent Systems (ICINIS), November 2012, pp. 49–52.
38. 38)
  - 27. Desmouliers, C., Oruklu, E., Saniie, J.: ‘Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s’, IET Circuits Devices Syst., 2011, 5, (4), pp. 321–328 (doi: 10.1049/iet-cds.2010.0259).
39. 39)
  - 17. Dobai, R., Sekanina, L.: ‘Towards evolvable systems based on the Xilinx Zynq platform’. IEEE Int. Conf. on Evolvable Systems (ICES), April 2013, pp. 89–95.

Hardware and software architectures for computationally efficient three-dimensional ultrasonic data compression

References

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